Circuit converts number represented as two level signal on n-bit lines to series of pulses on one of two lines, depending on sign of number. Converter accepts parallel binary input data and produces number of output pulses equal to number represented by input data

Hussey, J.

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November 1971	 Brief 71-10450 
NASA TECH BRIEF 
Manned Spacecraft Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield; Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Off i ce, NASA, Code KT, Washington, D.C. 20546. 
Digital Parallel-to-Series Pulse-Train Converter 
A new digital logic circuit can convert a number 
represented as a two-level signal on n-bit lines 
(parallel binary) to a series of pulses on one of two 
lines, depending on the sign of the number. This 
parallel-to-series pulse-train converter accepts 
parallel binary input data and produces a number 
of output pulses equal to the number represented 
by the input data. 
Circuits I and 2 (see Fig.'s I and 2) are two ver-
sions of the converter. Each version contains a 
binary counter, input-data sampling gates, address 
one-shot, stop logic, and clock enable logic. Circuit 
1 also contains a sign flip-flop, and circuit 2 in-
cludes both a sign flip-flop and a toggle flip-flop. 
The toggle flip-flop logic reduces the clock frequency 
by one-half. 
Data are loaded into the counter and the sign flip-
flop from a common data bus, using a 2 ps channel 
(continued overleaf) 
	
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CI- S 
Figure 3 
address (CHADD) pulse. The leading edge of the either circuit	 I	 or cirtuit 2 may be added to direct 
CHADD pulse initiates a I /S RESET pulse which a signal	 to the appropriate (plus or minus) output 
forces	 all	 flip-flops	 in	 the	 counter	 to	 reset.	 The line. 
trailing edge of the 2 js CHADD pulse then loads Note: 
the	 "one's"	 complement of the input-data magni- No additional documentation is available. Specific 
tude into the counter by sampling the inverted questions, however, may be directed to: 
put data. The trailing edge of the CHADD pulse Technology Utilization Officer 
also loads the input-data sign bit into the sign flip- Code JM7 
flop. Therefore, for any input data other than	 an Manned Spacecraft Center 
"all zeros," the STOP level goes false after the data Houston, Texas 77058 
are loaded. Reference: B71-10450 
The	 counter advances with 	 the	 trailing edge of 
each output pulse	 until the	 STOP level goes true. Patent status: 
The next CLK pulse	 resets the ENCLK flip-flop, No patent action is contemplated by NASA. 
inhibiting any further CLK pulses from appearing Source: J. Hussey of 
at the output. Grumman Aerospace Corp. 
If only the magnitude of the number is required, under contract to 
one	 output	 line	 is sufficient (see	 Fig.	 3).	 If sign	 as Manned Spacecraft Center 
well	 as	 magnitude	 is	 required,	 the	 sign	 logic	 of (MSC-12417)
Brief 71-10450	 CategoryOl 


Digital parallel-to-series pulse-train converter

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