Binary to decimal decoder logic circuit design with feedback control and display devic

Byrne, F.

English

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WASMIN~TON, D.C. e 
acnv to 
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Attantion8 Xi88 Wirmio M. Morgan 
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NASA Patent Case NO. a : 'w2'&$kZ"t6 
NOTE - If th is  patent covers an invention made by a corporate 
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the first page of the patent; hawlaver, the naaacr of the actual 
inventor (author) appears a t  the heading of Coluaur No. 1 of 
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https://ntrs.nasa.gov/search.jsp?R=19710015414 2020-03-17T02:58:58+00:00Z
Od. 20, 1870 F. BYRNE 3,535,497 
BCD TO DECIMAL DECODER 
F i l ed  June 21,  1967 2 Sheets-Sheet 1 
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3,535,491 United States Patent OBce ,,,, .., , ,, 
1 2 
nals into their decimal constituents, while utiIizing a mini- 
3,535,497 mum of components. 
BCD TO DECIMAL DECODER Another important object of the present inve~ition is lo 
Frank Byme, Cocoa Beach, Flia., assignor to the United provide a simple, inexpensive, and reliable decoder for States of America as represented by the Administrator converting BCD signals into decimal constituents, 
of the National Aeronautics and Space Administration 5 while preventing erroneous of means as- Filed June 21, 1967, Ser. No. 649,076 
Int. el. W03k 13/24,13/243 sociated with the decoder. 
U.S. Cl. 235-155 2 Claims Still another important object ol the present invention 
is to provide a simple decoder for converting BCD signals 
into their decimal constituents without having to transmit 
ABSTRACT OF THE DISCLOSURE the complement of the BCD signals. 
A decoder which utilizes a plurality of gates for decod- A further important object of the present invention i s  
ing binary signals into their decimal constituents. The de- to provide a decoder which utilizes feed-back signals from 
coder utilizes feed-back or inhibit signals for preventing certain preselected logic circuits for inhibiting the o p r a -  
15 tion of other logic circuits, thus eliminating the possibility erroneous decoding or displaying of the decimal con- 
of displaying erroneous signals. stituents. Other objects and advantages of this invention will be- 
come more apparent from a reading of the following de- 
The invention described herein was made by an em- tailed description and appended claims. taken in conjrrnc- 
ployee olf the United States Government and may be 20 tion with the accompanying drawings wherein: 
manufactured and used by or for the Government of the FIG. 1 is a schematic diagram oY a decoder constructcd 
United States of America for governmental purposes with- in accordance with the present invention for converting 
out the payment of any royalties thereon or therefor. binary coded decimal signals into their decimal constit- 
This invention relates to a decoder for converting uents; 
binary coded decimal signals into their decimal constitu- 25 FIG. 2 is a schematic diagram of one logic gating circcit 
ents, and more particularly to a decoder which utilizes utilized in the decoder; 
feed-back signals for preventing erroneous signals from FIG. 3 is a schematic diagram of another logic gating 
being displayed. circuit utilized in the decoder; and 
Heretofore, decoders provided for decoding binary FIG. 4 is a truth table illustrating the logic levels re- 
coded decimal l(BCD) signals into their decimal constit- 30 quired to activate the indicators associated with the logic. 
uents and displaying same required the complement of circuits. 
the binary coded decimal signal to be transmitted with the Referring now in more detail to the drawings. wherein 
signal. Such required the use of additional interconnecting like reference numerals designate identical or correspond- 
circuits which utilized either more logic circuits and/or ing parts throughout, and with to 1 ,  
additional interconnections. Instead of generating the 35 numeral 10 generally desfEnales a decoder con- 
complement of the binary coded decimal signal within the structed in accordance with the prerent invention. The de- 
decoder or transmitting the same over additional wires, coder shown in FIG. 1 illustrates the decimal constituentc 
the decoder constructed in accordance with the present or numerals 0 through 9 being displayed by appropriate 
invention utilizes unique decoded BCD values for partic- lamps. It  is to be understood, however. that other numeral.; 
ular decimal numbers. The Outputs of certain preselected 40 could be displayed in a similar manner. The decoder uti- 
logic circuits are fed back to the input of other preselected lizes a pair of "AND- logic gates 11 and 12, respectively, 
logic circuits to inhibit the activation of such. This elimi- the details of which are illustrated il FIGS. 2 and 3, 
nates the need of transmitting the complement of the Each of the logic gating circuits has some of input 
BCD signals over additional wires or utilizing additional conductors 13 through 16, respectively, connected thereto 
logic circuits. 45 Only the appropriate input conductors are connected to 
In accordance with the present invention, it has been the logic gating circuits for decoding a BCD 
found that the foregoing difficulties encountered in de- signal. The input conductors 13 thlough 16  are, in turn. 
coding BCD signals into their decimal constituents and connected to input leads 1 3 ~  through l B n ,  respectively, 
displaying such may be overcome by providing a novel upon which BCD signals are supplied from any suitable 
decoder. This decoder includes the lfollowine, basic parts: 50 source, such as from a computer. when a binary signal is 
(1) a logic gating circuit provided for each decimal con- supplied to input lead 13a such represents the valve of 2" 
stituent which is to be produced, (2) a display means con- which is equal to  1. A signal on the input lead 
nected to the output of each gating circuit being activated represents 21 which is equal to 2. A signal on the input 
responsive to selected binary input signals being supplied lead isa represents 2 2  which is equal to 4. A signal on 
to the respective gating circuit, (3) selected parallel input 55 the input lead represents 2 3  is equal to &, ~ h e  
leads connected to each gating circuit for receiving BCD appropriate value of the binary s;gnals being supplied 
signals in parallel form for activating a particular gating on the input leads 13 through 16 js illustrated in the 
circuit when the BCD signals make-up the decimal con- drawings. connected by lead 17 lo the olltput of the 
stituent for the particular gating circuit, (4)  feed-back logic gates 11 and 12, respectively, j s  a signal indicllting 
circuits connected to the Output of selected logic gates for 60 device, such as a lamp 18, which is illuminated when the 
supplying inhibit signals to certain logic gates for prevent- gating device to which it is connected is activated. 
ing activation of same when an inhibit signal is supplied other sides of the illuminating dev-ces are corlnected to 
thereto. Thus, a minimum number of input BCD signals ground or minus 6 volts depending on the gating circuit 
can be utilized to energize a display means while prevent- being utilized. Each of the illumin:,ting devices 18 have 
ing other display means from being erroneously energized. 65 printed thereon, a numeral representing the decimal value 
A logic gate is provided for each of the decimal constit- of the signals being supplied to the logic gates. In the 
uents 0 through 9 and a feed-back circuit is coupled to particular embodiment illustrated, only the decimal values 
the outputs of the logic gates provided for displaying the or decimal constituents 0 through 9 are represented. 
decimal constituents 0 ,7  and 9. A feed-back circuit is connected to the output of 
Accordingly, it is an important object olf the present 70 selected logic gates 11 and 12 for supplying an inhibit 
invention to provide a decoder which converts BCD sig- signal to certain logic gates for preventing activation of 
- 
 he logic :ales For example, a feed-back circuit includ- signal from the logic circuit associated with the lamp 18 
mg leiad 19 s~ipplies an inhibit signal from the output for displaying a "0" signal. 
of 1310 ic:ic gate 11 a~,sociated with the "0" circuit for in- In operation when a false signal or "0" voltage is on all 
hibitlng tile operatLor of the logic gates associated with four of the input leads 13 through 16, respectively, junc- 
lhe :.irrips representin2 decimal values 1, 2 and 4, respec- tion 23 goes to "0" volt?. When any one of the input 
ilveb. E i u s  when the logic gate BP associated with the leads has a true signal, or minus 6 volts supplied thereto, 
'i..mp "0'"s encrgized a minus 6 volt inhibit signal is sup- the junction 23 approaches minus 6 volts. When the junc- 
l:I~ed to ibe logic circr~its associated with lamps represent- tion 23 is at substantially zero volts the voltage at the base 
~xig decimal vaiues 1, 2 and 4. Particular voltages, such as 29 of transistor 30 goes slightly more positive than the 
'3'' volts :or a fdlse signal and minus 6 volts for a true vollage at the emitter electlode 31 turning on the tran- 
>lgni.i, v~-lI be used in expIaining the operation of the sistor. When the transistor is turned on current Rows 
~:,cocl,r, howevcr, it is to be noted that other suitable from ground illuminating the "0" lamp 18, and flows 
to:t;)ges bould be used. A feed-back lead 20 connects through the collector electrode 32, and out the emitter 
ihc o~itpil \ignai from the logic gate associated with the electrode 31. A minus 6 volt inhibit signal is fed back on 
'amp provicled for displaying a decimal value 7 when 15 lead 19 to an input of the logic circuits associated with 
Li~~kva:eil to the mput leads associated with lamps 3, 5 the lamps 1, 2 and 4. If there is a minus 6 volts or true 
and 6. A similar feed-back circuit including lead 21 signal on any one of the input leads, then the transistor 
couples t1-e output slgnal from the logic circuit associated 31 remains cut-off and there is a "0" voltage signal being 
with lamp 9 to an input lead of the logic gate associated fed back on the feed-back lead 19 which would not in- 
with lamp 8. When she logic gates associated with the 20 hibit the operation of the logic circugs receiving such 
I A I I I ~ S  0, 7 and 9 are activated a feed-back signal is fed signal. 
back to the above-mentioned logic circuits to inhibit the Logic circuit 12 is similar to  logic circuit 11 with the 
isperallon of such. Th IS, erroneous illumination of the dis- exception that the voltages are changed, and a PNP 
play l'xmps re2resenting the binary values O through 9 transistor 34 is utilized. The reason for using a pair of 
is prevented. 25 logic circuits 11 and 12, respectively, is to make optimum 
Rcfernng to the truth table illustrated in FIG. 4, it use of the feed-back and logic signals available. The diodes 
can be secn that when there is a false signal on all of the 35 have their cathodes connected to a common junction 
rnput Leads 13 ibrouzh 16, respectively, associated with 36 which is, in turn, connected through resistor 37 to a 
t l ~ e  ""6" lam;? such will activate the logic gate causing the negative 18 volt potential. Another resistor 38 is connected 
lamp to be illuminated. Since the logic gates associated 30 between junction 36 and junction 39. The junction 39 is 
ivith the lamps 1, 2 end 4 have signais being supplied to connected through a resistor 40 to a positive 12 volt po- 
the input thereof, which wonld normally activate such, tential. A base electrode 41 of the transistor 34 is also 
~t is necestary that ari inhibit signal which is in the form connected to junction 39. An emitter electrode 42 of the 
of a minut 6 voltage be supplied from the output of the transistor 34 is connected to ground by lead 43. Lamp 18 
logic gate associated with the "0" lamp to the input of 35 is connected between a negative 6 volt potential and a 
the logic gates assoc ated with the lamps 1, 2 and 4 to collector electrode 44 by means of lead 45. A feed-back 
illhibit their activation. Thus, in order for the logic gate lead 20 is also connected to the collector electrode 44 of 
associated with lamp 1 to be illuminated there would have the transistor 34. The particular logic circuit illustrated 
9 0  be a fdlse signal on the leads 14, 15 and 16, as well in FIG. 3 is that utilized in illuminating the decimal con- 
as a ""0"voitage being supplied over lead 19. 40 stituent of 7, and the other logic circuits 12 are identical 
The truth table ili~tstrates what signals are necessary with the exception of the feed-back leads and the number 
to i~iurninate the tamps associated with the logic cir- of input leads. 
cuirs For example, in order to illuminate the lamp 18 In operation, when a true signal of a minus 6 volts 
pro~ided for displaying a decimal value 8 it is necessary is placed on all of the input leads 13, 14 and 15 the volt- 
to have a [rile signal which represents a minus 6 volts on 45 age at junction 36 approaches a minus 6 volts. This causes 
fhe input lead 16 and a true feed-back signal of a minus 6 the transistor 34 to begin conducting and current flows 
volts on lead 21. In order to illuminate the lamp 18 pro- from the emitter electrode 42 through the collector elec- 
vided for displajing ;. decimal value 9 it is only necessary trode 44 iluminating lamp 18. A feed-back signal of "0" 
LO place 2 binary true signal of a minus 6 volts on the in- volts is supplied to an input terminal associated with the 
aut kads 13 and 16. espectively. I t  is noted that no other 50 logic circuits 12 which are provided for illuminating lamps 
lamp could be activated solely by true signals on these 3, 5 and 6, and inhibits the operation of such logic cir- 
two leads. cuits. When the transistor 34 is not conducting a minus 6 
FIG. 3 ;lIustrates the logic circuit 11 in schematic volt feed-back signal is supplied over lead 20 to the inputs 
form. Interposed in each of the input leads 13 through of the above-mentioned logic circuits allowing such to be 
16, respectively, is a diode 22. The anodes of the diodes 55 activated if the proper input signals are present on the 
22 ale connected lo a common junction 23 which is other input leads. 
coupled through a iesistor 24 to a positive 12 volt poten- While a preferred embodiment of the invention has 
tiai Another resistor 25 is connected between the junc- been described using specific terms and voltages, such de- 
lion 23 and a juncti>n 26. A negative 18 volt potential scription is for illustrative purposes only, and it is to be 
is applied to the junction 26 through resistor 27 and lead 60 understood that changes and variations may be made 
28, Junciron 26 is to the base electrode 29 of without departing from the spirit or scope of the follow* 
a NPN tiansistor 30. ?he emitter electrode 31 is con- 
nected to a negative six volt potential, while the collector 
1s connecteci by means of lead 33 to a lamp 18 which in the 
circurk illtist,ated is for illuminating the "a" decimal 
signal. The o h e r  side of the lamp is connected to  ground. 
The feed-back lead 19 is taken off the collector electrode 
32 and is ftcl  back to the appropriate logic circuit inputs. 
Ail of thc oiher logic circuits 11 are identical to the cir- 
curt iilostnated in FIG. 2 with the exception that the logic 
circuits piovided for illuminating the lamps for displaying 
the dccimil srgnals L ,  2 and 4 do not have a feed-back 
ledd. Aka, one of the input leads of each of the last- 
mzntioncll Yogic circa~its is used for receiving a feed-back 
ing claims. 
What is claimed is: 
1. A decoder for converting binary coded decimal sig- 
nals to their decimal constituents for display comprising: 
(A) a logic gating circuit provided for each decimal 
constituent which is to be produced: 
(B) a display means connected to the output of each 
gating circuit being activated responsive to selected 
binary input signals being supplied to said respective 
gating circuits; 
(C) selected parallel input leads connected to each of 
said gating circuits for receiving binary coded signals 
in parallel form for activating a particular gating 
circuit when said binary coded signals make-up the 
3,535,497 
5 G 
decimal constituent for said particular gating circuit; preventing other display means from bcmg c i ~ o ~ l e -  
(D) a plurality of feed-back circuits each connected to ously energized. 
the output of a selected logic gating circuit and being 2. The decodcr as set forth in claim 1 whereilz 
connected for supplying an inhibit signal to other of (A) each of said logic gating ciicuits i ~ c ' r ~ d e i  an 
said logic gating circuits for preventing activation of "AND" gate logic element; 
said other logic gating circuits when a selected logic (E) a transistor coupled to the output of sa;d "AND" 
gating circuit is activated; gate being activated responsive to a signal: paising 
(E) a logic gating circuit provided for each of the dec- through said "AND" gate, and 
imal constituents zero through nine; (C) said display means being co~ipled lo the oulp,:t of 
(F) said feed-back circuits being coupled to the outputs said transistor of cash logic g a t i ~ g  ciicuit. 
of said logic gating circuits provided for displaying 
ihe decimal constituents zero. seven and nine: References Cited 
(G) said feed-back circuits being connected to the 
outputs of said logic gating circuits provided for the 
seven constituent for supplying inhibit signals to the 
logic gating circuits provided for the three, five and 
six constituents when activated; and 
IH) said feed-back circuits being connected to the 
UNITED 
9/1944 
7/1965 
3/1967 
8/1967 
STATES PATENTS 
Wheeler -- -------- - 340-347 
Cohn et al. --------- 340-547 
Havens ------------ 340-347 
Lindarnan et al. ---- 235-155 
. , -
outputs of said logic gating circuits provided for R4AyNARD R. Primary Examiner the nine constituent for supplying inhibit signals to 20 
the logic gating circuit provided for the eight con- 6. R. EDWARDS, Assistant Examiner 
stituent; 
(I) whereby a minimum of input binary coded signals U.S. [el. X.,R. 
can be utilized to energize a display means while 34°-347 


BCD to decimal decoder Patent

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