Circuit diagram and operation of full binary adde

Schaefer, D. H.

English

NASA Technical Reports Server

July 20,1965 D. H. SCHAEFER 
FULL BINARY ADDER 
Filed Jan. 9, 1963 
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DAM0 H SCHAEFER 
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(NASA CR &R AD NU,) 3 (CATEGORY) 
https://ntrs.nasa.gov/search.jsp?R=19700025471 2020-03-17T02:01:39+00:00Z
3,196,261 Unifed States Patent Ofice ,,,, , ,, ,, 
1 2 
the advantages of sin~ilarly employed full binary addcrs; 
3,196,261 which utilizes less complex circuitry than most prior full 
FULL BPNARY ADDER binary adders; which does not require that the comple- 
David & Schaefer, Oxon Mill, Md.9  POP fo the united merits of the inputs be obtained; and which is stable over States of America as represented by the Adn~inistrator 
of the National Aeronautics and Space Administration temperature and "Itage fluctuations' 
Filed Jan. 9, 1963, Ser. No. 250,451 The preferred embodiment circuitry disclosed as in- 
8 Claims. (el. 235-176) corporating the invention utilizes the presences and ab- 
(Granted under Title 35, U.S. Code (1952), sec. 266) sences of pulses to represent "0's" and "1's." This cir- 
cuitry consists of only four diodes, six transistors, and 
The invention described herein may be manufactured 10 nine resistors. 
and used by or for the Government of the United St:ttcs The novel features of the invention as well as the invcn- 
of America for governmental purposes without thc pay- tion itself, hoth as to its organization and method of 
ment of royalties thcron or therefor. operation, will best be understood from the following 
The invention relates generally to an adder and more description, when read in connection with the accompaay- 
particularly to an improved full binary adder such as used 15 ing drawings, in which: 
in computing or data processing equipment. FIG. 1 is a block diagram of the invention; and 
When it is desired to add two binary numbers (augend FIG. 2 is a schematic diagram of the preferred em- 
number and addend number) a full binary adder is needed bodiment circuitry which incorporates the invention. 
for each binary place. A full binary adder is a device Referring now to FIG. 1 there is shown an "or" gate 
which will add three binary digits (bits) and produce a 20 12 having input terminals 10 and 11. Input signals A 
sum output (S) and a carry output (C,). The three and B, which are in the form of the presence or the ab- 
binary input bits received by an adder for a particular sence of pulses, are applied to input terminals 10 and 11. 
binary place are the augend bit (A) and the addend bit The presence of a pulse represents a "1" and the absence 
(B) for this binary place, and the carry bit (C) produced of a pulse represents a "0." As is well known in the art,' 
as the carry output (C,) by the adder for the next less 25 a pulse will be present at the output of "or" gate 12 if a t  
significant binary place. A full binary adder must satisfy any instant there is a pulse present at either input terminal 
the following truth table. 10 or 11, or if pulses are present at both input terminals 
10 and 11. l'he output of "or" gate 32 is applied to the 
non-dotted input of an "and inhibit" gate 13; and inputs 
30 A and B are applied to the two dotted inputs of "and 
inhibit" gate 13. An "and inhibit" gate is a binary device 
having one non-dotted input, two dotted inputs, and an 
output. It will produce a pulse at its output if a pulse 
is present at its nondotted input and if pulses are not 
35 present at both of its dotted inputs. Therefore, a pulse 
will be present at the output of gate 13 if there is a pulse 
present at its nondotted input and if pulses are not present 
a t  both of its dotted inputs. 
This truth table shows in its first three columns the eight Now consider the combined functions of gates 12 and possible combinations of inputs A, B, and C .  The fourth 40 13. A pulse will be present a t  the output of gate 13 when- 
column shows the S output for each of these eight cQm- ever there is a pulse present at either input terminal 10 
binations, and the fifth column shows the C, output for or 11 if pulses are not simultaneo~sly present at both of 
each of these eight combinations. these terminals. This combined function of gates 12 and 
As will be evident from the following discussion, the 13 is called an or" function and the combined 
above truth table complies with the rules for the addition q5 structure of gates 12 and 13 is called an "exclusive or" 
of three binary digits. If three binary digits are added, gate. 
there are eight possible combinations of the three digits. Gate 14 is an "or" gate identical to gate 12 and gate 
These eight combinations together with the sum digit and 15 is an uand inhibit,, gate identical to gate 13. Gates 
the carry digit for each combination follows: O + O + O = O  14 and 15 are also connected to form an ~Lexclusive or" 
with a carry of 0; 1+0+0=O-!-l-k0=0+0+1=1 with a 50 gate in the same way that gates 12 and 13 are connected 
carry of 0; I+  1+0=l+O+ l=O+ 1 + l = 0  with a carry to form an or" gate. The two inputs applied 
and 1+1$-1=1 with a carry The first cOmbi- to  gate 14 are the output of gate 13 and the carry input '2 
nation is shown by the first row of the truth table; the which is applied to an input terminal 16. ahefe will be 
next three combinations are shown by the second, third, produced, at an output terminal 17, a sum output S which 
and fifth rows of the truth table; the next three combina- 55 will follow the truth table for binary addition referred 
tions are shown by the fourth, sixth, and seventh rows of to earlier in this specification. ~f the eight 
the truth table; and the last combination is shown by the of input signals A, B and C, by the first three last row of the truth table. columns of the truth table, are applied to input terminals The "0's'' or "1's" that are either applied to or pro- 10, 11, and 16 respectively, then there will be produced, 
by a binary adder can be 'Vresented by any- 60 at output terminal 17, outputs which will correspond to 
thing that has two mutually exc1usive conditions. For the fourth column s of the truth 
example, they can be represent& by the presences and The C input at terminal 16, in addition to being 
the absences of pulses; by two different voltage levels; by to gates 14 and 15, is applied to the dotted or inverted 
switches that are either opened or closed; etc. input of an "inhibit" gate 18. The output of gate 13, in 
Many prior art full binary adders have certain dis- 65 addition to being applied to gate 14, is applied to the non- 
advantages that they have cOm~lex circuitry dotted or non-inverted input of gate 18, As is known 
utilizing many components; they sometime require that in the prior a*, there will be a pulse present at the output 
the complements of the inputs be obtained which make of winhibic, gate 18 if fiere is a pulse present its non- 
the circuitry even more complex; and oftentimes they dotted input and if there is no pulse present at its dotted 
are not stable over temperature and voltage fluctuations. 70 input. An "inhibit" gate can be thought of as an "and" 
  he general purpose of the present invention is to pro- gate with one of its inputs inverted before being applied 
vide an improved full binary adder which embraces a11 to it. 
\ 
3,106,261 
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The output of gate 18 is applied to the dotted or in- the input terminal 16 and the collector of transistor 24, 
verted input of an "inhibit" gate 19. The output of gate transistors 31 and 32 will conduct and output terminal 17 
12, in addition to being applied to gate 13, is applied to will be connected to ground. 
the non-dotted or non-inverted input of gate 19. There The collector of transistor 24 is connected through a 
will be a pulse present at the output terminal 20 of gate 5 resistor 35 to the collector of an NPN transistor 36 and 
19 if there is a pulse present at its nondotted input and to the base of an NPN transistor 37. The emitters of 
if there is no pulse present at its dotted input. The output transistors 36 and 37 are connected to ground. Input 
poduced at terminal 20 is the carry output C,  shown terminal 16 is connected through a resistor 38 to the base 
by the truth table for binary addition referred to earlier of transistor 36. The cathodes of diodes 21 and 22 are 
in this specification. Tf the eight combinations of input 10 connected through a resistor 39 to the collector of tran- 
signals A, B and C, shown by the first three columns of sistor 37 and to output terminal 20. Resistors 35 and 
the truth table, are applied to input terminals 10, 11, and 38, and transistor 36 f o ~ m  "inhibit" gate 18. A pulse 
16, respectively, then there will be produced, at output will be present at the collector of transistor 36 if there 
terminal 20, output signals which will correspond to the is a pulse present at the collector of transistor 24 and if 
fifth column C, of the truth table. 15 there is no pulse present at input terminal 16. If there 
A complete operat~on of a full binary adder defined is a pulse present at input terminal 16, transistor 36 will 
by the block diagram in FIG. 1 will now be described. conduct and connect the collector of transistor 36 to 
This description will be made on the assumption that a ground. 
pulse is present a t  input A, no pulse is present at input B, Resistor 39 and transistor 37 form "inhibit" gate 19. 
and a pulse is present at input C. This combination of 20 A pulse will be present at output terminal 20 if there is 
inputs is one of eight possible combinations of inputs and a pulse present at the cathodes of diodes 21 and 22, and 
it corresponds to the sixth row from the top of the truth if there is no pulse present at the collector of transistor 
table referred to  earlier. For this assumed combination 36. If there is a pulse present a t  the collector of tran- 
of inputs, a pulse will be present at the output of gate sistor 36, transistor 37 will conduct and connect output 
12; a pulse will be present at the output of gate 13; a 25 terminal 20 to ground. 
pulse will be present at tbe output of gate 14; no pulse Obviously numerous modifications or variations of the 
will be present at output terminal 17 since pulses will be present invention are possible in light of the above teach- 
present at both the output of gate 13 and the input ter- ings. For example, different circuitry than that dis- 
minal 16; no pulse will be present at the output of gate closed in FIG. 2 may be used for the "or" gates, the 
18 since there is a pulse present at input terminal 16; and 30 "inhibit" gates, or the "and inhibit" gates. It is therefore 
a pulse will be present a t  output terminal 20. It  should to be understood that within the scope of the appended 
be noted that no output at terminal 17 and an output at claims the invention may be practiced otherwise than as 
terminal 20 satisfies the truth table for the assurned com- specifically described herein. 
bination of inputs. What is claimed is: 
Referring now to FIG. 2, there is shown a schematic 35 1. A full binary adder comprising: first and second 
diagram of the circuitry represented by the blocks in the "exclusive or" gates with each having first and second 
block diagram of FIG. 1. The dotted rectangles in FIG. input terminals and an output terminal and with at least 
2 encloses the circuitry represented by the corresponding the first "exclusive or" gate including an "or" gate; means 
blocks in FIG. 1. Input terminal PO is connected to  the for connecting two binary input signals to the two input 
anode of diode 21, and input terminal 11 is connected 40 terminals of the first "exclusive or" gate and to said 
to the anode of a diode 22. The cathodes of diodes 21 "or" gate; means for connecting a third binary input signal 
and 22 are connected together to form "or" gate 12. and the output signal from the output terminal of the first 
The cathodes of diodes 28 and 22 are connected through "exclusive or" gate to the two input terminals of the 
a resistor 23 to the collector of an NPN transistor 24. second "exclusive or" gate; first and second "inhibit" 
The emitter of transistor 24 is connected to the ~ 0 l l e ~ t o r  45 gates with each having one inverted and one non-inverted 
of an NPN transistor 25. The emitter of transistor 25 input terminal and with each having an output terminal; 
is connected to ground. Input terminal 20 is connected means for connecting said third input signal to the in- 
through a resistor 26 to the base of transistor 24; and verted input terminal of the first "inhibit" gate; means for 
input terminal 11 is connected through a resistor 27 to connecting the output signal from the first "exclusive orw 
the base of transistor 25. This circuitry forms "and in- 50 gate to the non-inverted input terminal of the first 'Tn- 
hibit" gate 13. A pulse will be present at the collector hibit" gate; means for connecting the output signal from 
of transistor 24 whenever there is a pulse at the cathodes the first "inhibit" gate to the inverted input terminal 
of diodes 21 and 22 if pulses are not sirnultaneousl~ pres- of the second "inhibit" gate; and means for connecting 
ent at both input terminals 10 and 11. Pf p ~ l s e s  are PreS- the output signal from the "or" gate to the non-invefied 
ent at both input terminals 18 and 11, transistors 24 and 55 input terminal of the second 'Tn&bit" gate whereby the 
25 will conduct and the collector of transistor 24 will output signal a t  the output terminal of the second "ex- 
be connected to ground. clusive or" gate is the sum output signal and the output 
Input terminal 16 is connected to the anode of a diode signal a t  the output terminal of the second "inhibit" gate 
28; and the collector of transistor 24 is connected to the is the carry output signal. 
anode of a diode 29. The cathodes of diodes 28 and 29 60 2. A full binary adder as in claim 1 wherein 
are connected together to form "or" gate 14. said first "exclusive or" gates consists of: a first resistor 
The 28 and 29 are connected having first and second terminals; a first diode connected 
through a resistor 30 to the collector of an NPN tran- between the first input terminal and the first terminal of 
sistor 31. The emitter of transistor 31 is connected to the first resistor; a second diode connected between the 
the collector of an NPN transistor 32. The emitter of 65 second input terminal and the first terminal of the first 
transistor 32 is connected ground. Input l6 resistor; a first transistor with its collector to 
is connected through a resistor 33 to the base of transistor 
3P; and the collector of transistor 24 is the second terminal of the first resistor; a second tran- 
a resistor 34 lo the base of transistor 32. Output termi- sistor with its collector connected to the emitter of the 
rial 1, is connected to *he collector of transistor 31. -j=his 70 first transistor and with its emitter connected to ground; 
circuitry forms inhibit- gate 15. A pulse will be a second resistor connected between one of the input ter- 
present at output terminal 17 whenever there is a pulse minals and the base of the first transistor; and a third 
at the cathodes of diodes 28 and 29 if pulses are not simul- resistor connected between the second input terminal and 
taneously present at both the input terminal 16 and the the base of the second transistor. 
collector of transistor 24. If pulses are present at both 75 3. A full binary adder as claimed in clitim 1 wherein 
3,196,261 
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s:iid first "inhibit" gate consists of: a first transistor hav- 7. In :I full hin:~ry adder, means for producing a "carry 
ing its emitter connected to ground; a first resistor con- output" from the three inputs applied to the full binary 
netted between the collector of the first transistor and adder comprising: means for producing the "or" and the 
the output terminal of the first "exclusive or" gate; and "exclusive or" functions from two of the three inputs; 
a second resistor connected between the base of the first 5 a first "inhibit" gate having an inverted input and a non- 
transistor and the third input whereby the output of the inverted input connected to receive the third input a t  its 
first "inhibit" gate is produced at the coIlector of the first inverted input and the produced "exclusive or" function 
transistor. at its non-inverted input; and a second "inhibit" gate hav- 
4. A full binary adder as claimed in claim 3 wherein ing an inverted input and a non-inverted input connected 
said second "inhibit" gate consists of: a second transistor 10 to receive at its inverted inpxt the output from the first 
with its emitter connected to ground and with its base "inhibit" gate and connected to receive at its non-inverted 
connected to the collector of the first transistor; and a input the produced "or" function whereby the output of 
third resistor connected between the collector of the the second "inhibit" gate is. the carry output. 
second transistor and the output of said "or" gate whereby 8. A full binary adder having three inputs comprising: 
the carry output is produced at the collector of the second 15 means for producing "or" and first "exclusive or" func- 
transistor. tions from two of the three inputs; a first "inhibit" gate 
5. A full binary adder as claimed in claim E wherein having an inverted input and a non-inverted input con- 
said first "exclusive or" gate comprises: an "or" gate nected to receive the third input at its inverted input and 
with its inputs connected to the two input terminals of the produced "exclusive or" function at its non-inverted 
the "exclusive or" gate; and an "and inhibit" gate with 20 input; a second "inhibit" gate having an inverted input 
its two dotted inputs connected to the two input termi- and a non-inverted input connected to receive at its in- 
nals and with its non-dotted input connected to the output verted input the output from the first "inhibit" gate and 
of the "or" gate. connected to receive at  its non-inverted input the pro- 
6.  A full binary adder as claimed in claim 5 wherein duced "or" function; and a means for producing a second 
said "and inhibit" gate comprises: a first resistor con- 25 "exclusive or" function from the third input and the first 
nected between the output of the "or" gate and the c01- or" function whereby the second "exclusive 
lector of a first transistor; a second transistor with its or" function is the sum output and the output of the 
emitter connected to ground and with its collector con- second -inhibit" gate is the carry output. 
nected to the emitter of the first transistor; a second 
resistor connected between one of the two input termi- 30 No references cited. 
nals and the base of the first transistor; and a third re- 
sistor connected between the other of the two input ter- MALCOLM A. MORRISON, Primary Examiner. 
minals and the base of the second transistor. 


Full binary adder Patent

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