Integration loop, with narrow bandwidth and long response time, integrates phase estimate of sampling loop, resulting in slower but less jittery response to phase step changes. Sampling loop has wide bandwidth and quick response to phase steps of burst sync interval

Balcewicz, J. F.

English

NASA Technical Reports Server

September 1971	 Brief 71-10349 
NASA TECH BRIEF 
Goddard Space Flight Center
	
_4V 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
Double Phase-Lock Loop With Rapid Transient Response: A Concept 
The problem: 
In a burst synchronized, time-division-multi-
plexed communication system, the duration of the 
sync burst is on the order of one microsecond. A 
single	 narrow band
	 second-order	 phase-lock 
Sampling Loop: Rapidly Received	 Acquires Phase Changes Signal 
(Burst Sync)
	 R = 163 12 
4.71 MHz	
12.02 kIl
48011 
0.1 
4.71 MHz 
VCO 
Jr To Bit Timing and Data Demodulation 
Integration Loop: Gradually Acquires 
Phase Changes, Responds 600 Times 
More Slowly than Upper Loop 
Double Loop Circuit: Extracts Bit-Timing 
from a Burst-Synchronized TOM Signal
loop cannot respond fast enough during the sync 
interval to remain in synchronism with the received 
signal. 
The solution: 
Two second-order phase-lock loops could be em-
ployed. The sampling loop would have a wide band-
width and quick response to the phase steps of 
the burst sync interval. The integration loop, 
with a narrow bandwidth and correspondingly 
long response time, would integrate the phase estimate 
of the sampling loop, and the result would be a 
slower but less jittery response to the phase step 
changes. 
How it's done: 
During a sync interval, the switch in the sampling 
loop (see fig.) is closed, charging the capacitor 
through resistor R. The voltage change on the 
capacitor changes the frequency of the voltage-
controlled oscillator (VCO) to keep it in phase 
with the received signal. After the sync interval, 
the switch is opened and the charge on the capacitor 
maintains the VCO frequency until the next sync 
interval, when the capacitor voltage and VCO fre-
quency are changed again, keeping theni locked 
to the received signal. The maximum timing error 
that develops in the sampling loop is only that 
error which results from frequency drift during the 
interval between sync bursts. 
The integration loop is continually tracking to 
find and lock onto the sampling loop VCO fre-
quency. Since the integration loop responds more 
slowly, it can never be in phase lock, but will 
always be within a certain phase difference. This 
phase difference can be made as large or as small 
as desired by varying the integration loop's 
ciiiIintied ne rkal 
During 
Closes	 500 Pf[ 
•1 Sync = 
This documett was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately ownedrights.
https://ntrs.nasa.gov/search.jsp?R=19710000347 2020-03-17T02:28:12+00:00Z
response time. In most cases, the limit on the 
phase difference is determined by the maximum 
allowable timing error in the system. The double 
loop provides a timing reference within 1% of the 
received signal timing and has a signal-to-noise 
ratio which is 30 dB greater than a reference pro-
duced by a single loop. 
Note: 
No additional documentation is available. Specific 
questions, however, may be directed to: 
Technology Utilization Officer 
Code 207.1 
Goddard Space Flight Center 
Greenbelt, Maryland 
Reference: B71-10349
Patent status: 
No patent action is contemplated by NASA. 
Source: J. F. Balcewjcz of

Astro-Electronics Div.

Radio Corporation of America

under contract to

Goddard Space Flight Center

(GSC- 10864)
[1 
S 
Brief 71-10349
Category 01


Double phase-lock loop with rapid transient response - A concept

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