High speed, self-clocking single channel control and data link apparatus interfaces between two computers. This combined system reduces data errors

Layland, J. W.

Martin, W. L.

Zygiebaum, A. I.

English

NASA Technical Reports Server

September 1970	 Brief 70-10163 
NASA TECH BRIEF 
NASA Tech  Briefs announce new technology derived from the U.S. space program. They are issued to encourage commercial 
application. Tech Briefs are available on a subscription basis from the Clearinghouse for Federal Scientific and Technical 
Information, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
	
-------
	 2	 T-
Communications Link for SDS 900 Series Computers 
POT Connector  
	
ff
Data 	 1 Parity
Data Load
EOMSDS	 _______Parallel I _________
900 Series
____	 _____To Computer	 Serial 
—111, 
T	 IPIN	 'lnterrupts	 tlIolI 	 ge I Outputor
Trans-
ceiver I 
Transmit ____________ Counter  Clock
I 
I
Error 
Message 
Generator 
Error 4 Signal 
-
Check Conchtioi 
Serial To 
Parallel - ______________________ 
Converter
Control 
Decode 
Data Load
Input 
-ri4== Clock
The problem: 
To design a combined system of two or more com-
puters with a minimum number of connections in order 
to reduce data errors substantially. 
The solution: 
Develop a high speed, self-clocking single channel 
control and data link apparatus to interface between 
the two computers. 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
How it's done: 
The block diagram above depicts the interfacing 
circuitry associated with the computer at one end of 
the communications link. Identical circuitry is 
associated with the computer at the other end of the 
link. 
The transmitted output from the remote computer 
is received in serial form by the transceiver shown 
-	 (continued overleaf) 
-
Government assumes any liability resulting from the use of the 
information contained in this document, or'warrants that such use 
will be free fràm privately owned.rights. 
https://ntrs.nasa.gov/search.jsp?R=19700000157 2020-03-17T00:27:54+00:00Z
at the far right in. the diagram. Timing circuits de-
termine if. .a complete data and control message has 
been received and check the composite signal for 
correct parity and rate If errors are present an error 
control message is sent back to the originating com-
puter If the signal is normal it is converted from 
series to parallel form and input to the local computer 
(PIN), which then acts on the control and data com-
ponents to perform the task programmed. 
To transmit, the data in parallel output form (POT) 
is fed through the energize output medium (EOM) 
decode to the parallel-to-serial converter. The EOM 
senses the start of a transmission and activates the 
appropriate equipment to route the data to the trans-
ceiver. The serial data, together with control, codes 
and a parity bit, are fed ' to the' output driver which 
converts the pulses to a three-level form (+5 volts for 
the I state; —5 volts for the 0). Transmission of the 
data in this form femoves the.. necessity of transmit -
ting a clock signal on a separate channel.
Note: 
Requests for further information may be directed 
to:
Technqlogy Utilization Officer 
NASA Pasd'e'na Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: TSP70-10163 
Patent status:.. 
No patentaction is contemplated by NASA. 
Source Arthur I Zygiebaum James W Layland 
and Warren L. Martin of 
Caltech/JPL 
under contract to 
.NASA Pasadena Office 
(NPO-11161) 
Brief 70- 10163
	 çategory.Q2


Communications link for SDS 900 series computers

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server