Register requiring two integrated circuits per stage has nominal power dissipation of 3.5 mW per stage, its use eliminates reset pulse, allowing data transfer to occur in less than 1 microsecond, and eliminates power application to both right and left portions of the register simultaneously

Cliff, R. A.

English

NASA Technical Reports Server

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August 1971	 Brief 7l-I0322 
S
NASA TECH BRIEF 
Goddard Space Flight Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the. Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546.
•. 
Novel Shift Register Eliminates Logic Gates
and Power Switching Circuits 
The right/left shift register shown in the block 
diagram transfers binary data between various 
storage registers in a digital computer without the 
need for complex power switching circuits and
the number of components and one-half the power 
of conventional versions. Significant advantages 
include: (I) elimination of a reset pulse, allowing 
data transfer to take place in a much shorter time 
logic gates. Elimination of these circuit requirements 
reduces the weight and power requirements, and 
increases the reliability of the computer. 
The register requires only two integrated circuits 
per stage and has a nominal power dissipation of 
3.5 mW per stage. The entire register uses two-thirds
interval—less than 1i second; and (2) elimination of 
power application to both portions of the register 
simultaneously. 
In operation, power is applied to either side of 
the register. When power is applied to the right-
shifting (RS) register, the entire assembly acts as an 
(continued overleaf) 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19710000320 2020-03-17T02:21:17+00:00Z
RS register; serial data enters at the right input 
terminals and leaves at the right output terminals. 
When power is applied to the left-shifting (LS) 
register, an analogous sequence occurs. Conversion 
from right to left operation is achieved simply by 
switching the input power. 
At the time of conversion, the data in the combined 
right/left register is unaltered. If the RS register 
is energized and one of its stages contains a "1," the 
Q output of that stage holds the Q output of the 
corresponding LS register stage at a positive potential. 
Similarly, the Q output of the RS register flip-flop 
holds the corresponding Q output of the LS register 
at ground potential. If the flip-flop of the RS 
register contains a "0," the potentials of Q and Q are 
reversed, but the mode of operation is the same. 
Data transfer between registers is achieved by 
energizing the RS register and then de-energizing the
LS register. Power need not be applied simultaneously 
to both registers in order to transfer the data because 
the residual capacitance in the flip-flops maintains 
the logic state while power is being switched. 
Note: 
No additional documentation is available. Specific 
questions, however, may be directed to: 
Technology Utilization Officer 
Goddard Space Flight Center 
Code 207.1 
Greenbelt, Maryland 20771 
Reference: B71-10322 
Patent status: 
No patent action is contemplated by NASA. 
Source: Rodger A. Cliff

Goddard Space Flight Center

(GSC-10517)
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. 
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Brief 71-10322 Category 01


Novel shift register eliminates logic gates and power switching circuits

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