Binary to binary-coded decimal converter using single set of logic circuits notwithstanding number of shift register decade

Imlay, E. H.

English

NASA Technical Reports Server

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https://ntrs.nasa.gov/search.jsp?R=19700026107 2020-03-17T02:06:08+00:00Z

March 2, 1965 
BINARY TO BINARY-CODED-DECIMAL CONVERTER 
u 
FIG. 3 
A = SAMPLE COMMAND 
B = EXT. BINARY DIGIT 
C = CLEAR COMMAND 
S = SHIFT COMMAND 
N, = BINARY I IN REGISTER STAGE (NH) FIG. 4 
%a = BINARY I IN PREVIOUS REGISTER STAGE (N,.,) 
lWUVTOR 
Edward W .  lrnlay 
BY 
Attorneys 


3,172,087 
3 4 
dorlbling onc. N - I  times. or hy multiplying the onc in After the first three binary digits have been entcred 
the binary ni~rnbcr hy two, N- l times. into the complement-shift register 12, circuits designated 
It is common knowledge that a shift register can readi- as sense-and-col~iple~~lent circuits 14 sense these first three 
ly multiply n binary number by two by shifting the en- digits to determine whether or not their value is five or 
tire number within the register once towards the most 5 greater. If the value is fivc or greater, then three is 
significant cnd of the register. This preliminarily requires added to the number in the con~plenient-shift register, 
that arbitrary valucs of multiples. of two be assigned to and the complement-shift register contents are shifted one 
each one of the register stages. A shift register may also digit position in the increasing binary direction. If the 
be made to hold a hinary-coded-decimal number by the v a l ~ ~ e  in the complement register is not five or grcatcr, 
simple expedient of assigning four stages to  represent the 10 then the contents are simply shifted one binary digit posi- 
value of a decade in binary-code form. Referring to  tion in the increasing binary order direction. Since under 
FIGURE 1. this may be readily seen, if it is assumed that the assumed example the value of the binary number . 
the rectangle 10 represents a shift register having 12 now in the complement-shift registcr exceeds five, the 
stages. The twelve stages may be divided into three value three is added thereto, converting the number in the 
decades of four stages each, respectively, units, tens, and 1 .j complement-shift register to 101 0. 
htlndreds. and the stages within a decade may have the The next step is to shift both the shift register and the 
value one. two, four, eight. complement-shift register one binary-bit position. When 
The shift register 10 also may he made to contain a this occurs, the one digit in the eight position of the CoJii- 
hinary nrrrilher. and a binary number is shown entered plement-shift register is inserted in the number 12 slagc 
therein in slngt.s 4 throllgh 12, which are inversely given 3 1  of the shift register, thc zcro, which \vas in iiie i~lim!?er 
the vnl~!cs i'rorn 2" to 27. 13y way of example, the binary one stage of the shift register., is insertcd into the onc 
niririhc~: I I I Oir l  10 . i a c i \ \ i ~  in the shift register EO equ:lls posilion of complement-shift register. In other wo!-(Is, 
2 3 0  in I I K  Jt<in>:il : .v \~~!IIJ .  hot), shift registcr and complcmenl-shift i.cgis!cr a r c  
In a~1~0J'dnnce \bilk) j h i ~  itlkention. a cornplemcnt-shift together, with the o\~crtlow froin the co!?lpicmenl- 
register 12 may incltltle four st;igcs. having assigned there- 2.; shift register being circulalecl back into the shift rcgisier. 
to the valnes. I-cspccliitiy. one, LN'o. four, and eight. As Now, another inspection step occurs. Since thc v;ilue 
will Ile dcscribctl i~ iore  fully subsequently herein, the of the number now in the co~nplemcnt-sliif? register is 
contents of the shift regisicr 10 are successively entered less than fivc, no addition of three is ncccssnry, anti a 
into the con>p]cmenl-shift register 12, lo be operatcd shift operation occurs which chanzes the value of the 
thereon in order that a conversion to binary-coded-deci- number in the shift registcr from 0100 to 1000, or fr(?i?~ 
mal may occur. four to eight. Of course, the overflow from the comple- 
-- 
................ 
............................ ........ I 
............................ Sl~ilt ........... 1 0 
Arid 3 . .  ..... ............................ 1 O 
............................ ............ Shift 0 1  
............ ............ . . id ,  ....... 0 
Sliilt ............ .............. . 1 
Table 1 shows the successive steps which occur in the n~ent-shift registcr is now inserted into the shift register, 
embodiment of the invention for converting a binary following the one which was previously inserted therein. 
number to a binary-decimal-coded number. The num- 53 Since the number in the complen~cnt-shift register now 
ber taken, by way of example, is the number shown in exceeds five, three is added thereto, and thcn the coin- 
the shift register 10, which equals 230. The binary num- piement-shift register and shift register are shifted one 
bes is entered into the shift register so that each bit is binary bit position. This results in the number 01 1 1  he- 
stored in a stage which is assigned to represent a binary ing in the complement-shift registcr, which exceeds f i v ~ .  
digit of the proper order. The binary digits are to be 60 and the number 101 is now in the shift regisier. The addi- 
shifted serially, highest-order digit first, into the comple- tion of three to the number in the complement-shift 
men1 register 12. Assume a t  the outset that the first three register results in the number 1010 n0.N being in the com- 
binary digits are shifted into the complement-shift regis- plement register. Upon the occurrence of the shift opera- 
ter 12. In  Table 1 this step is designated as a read-in. tion, the number in thc coniplement-shift register now 
At the same time that the first three binary digits of the 65 becomes 0101, and the number in the shift register re- 
shift register 10 are shifted into the complement-shift ceived from the shift register is now 1011. 
register, the other binary digits will also be shifted, so The number in the complemenl-shift register is five or 
that the fourth binary digit is ready to be entered into greater, and, therefore, the value three is added thereio. 
the complement-shift register upon the next shift opcra- This converts the number in the complement-shift resister 
tion. Under the column designated "'In Complement- 7 0  to 1000. Upon the occurrence of the shift operation, thc 
Shift Register," there is shown the contents of the com- number in the complement-shift register is 0000, and the 
plement-shift register at each step of the operation. Under number in the shift registcr is 1011 1. It should he notcti 
the column "In Register," there is shown the contents of thnl the n ~ l i i ~ l ~ e r  now in the complement register rcpi.e- 
the register for the corrcspondi~?g contents of the com- scnts the units decade in hinary-cotled-tlecinl:il arid i; th,: 
plement-shift register. ;.j unils valuc of thc dccimal equivalent of thc original 
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Circulate ....... 
Add3  .......... 
Shif t  ........... 
Shif t  .......... 
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Binary to binary-coded-decimal converter Patent

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