RC transistor circuit to indicate each pulse of pulse train and occurrence of nth puls

Rehage, J. R.

English

NASA Technical Reports Server

REPLY ro 
ATTN OF: GP 
NATIONAL AERONAUTICS AND SPACE ADM INISTRATION 
WASHINGTON, D.C. 20546 
October 15, 1970 
TO : USI/Scientific & Technical Information Division 
Attention: Miss Winnie M. Morgan 
FROM : GP/Office of Assistant General 
Counsel for Patent Matters 
SUBJECT: Announcement of NASA-Owned 
U , S ,  Patents in STAR 
In accordance with the procedures contained in the Code GP 
to Code US1 memorandum on this subject, dated June 8, 1970, 
the attached NASA-owned U , S ,  patent is being forwarded for 
abstracting and announcement in NASA STAR. 
The following information is provided: 
U,S. Patent No. E 3,287,640 
Corporate Source Marshall Space Flight Center 
Supplementary 
Corporate Source 
NASA Patent Case NO, : ~ ~ ~ - 0 0 9 0 6  
GaGle Parker 
Enclosure: 
Copy of Patent 
NASA-HQ 
https://ntrs.nasa.gov/search.jsp?R=19700032339 2020-03-17T02:12:14+00:00Z
.... 
COUNTING C TAWEOUSLY INDICATES 
TEB 0 
JON RICHARD REHAGE, 
 OR . .  
B 
BT TORNEYS 
3,287,640 
P W E  COUNTING CWCUX" WHICH SVdUI.a%'AT'd% 
WSLY INDICATES OCCURRENCE OF THE 
n W  PULSE 
Jon,Richard Rehaage, Mndison, Ma., assignor Po &e United 
Sates of America as represented by the A d m X h t o r  
of the National Aeronautics and Space Administration 
Tied Mar. 12,1963, br. No. 2646331 
6 Ciaims. (el. 324-113) 
of curves descriptive of 
the invention shown in FIGURE I. 
1 consists basically of preamplifier B 
impedance changing circuit B8 and indicator circuit 29. 
Preamplifier 18 is a transistor amplifier stage ernploy- 
ing as an active element transistor 21 (e.g., ZNW). 
The base of transistor 21 is biased by means of a voltage 
10 divider network consisting of voltage dropping or current 
The invention described herein may be manufactured limiting resistor 22 (e.g., 82K ohms) and input resistor 
and =sed by or for the Government of the United States (e.gl 8.2K ohms) connected in series at terminal 
of America for governmental purposes without the pay- and terminal 26 connects to the base of transistor 28. 
ment of any royalties thereon or therefor. Input to the circuit is applied across terminals 
This invention relates to electrical indicating systems 16 30 and is fed through capacitor 3% (e.g., 10 mf.) to the 
and particularly to a system for indicating, as by record- base of transistor 21. Plus terminal 34 of bias source 
ing, each cycle or pulse of a train of pulses and a signal 35 is connected to a terminal of resistor 
denoting that the nth !pulse has occurred. tive terminal of s o m e  35 connects to a common ground 
There are a number of application in which it is neces- terminal 36, as does the emitter of transistor 21. 
sary to both examine or view each of a series or train 20 With the application of an alternating current input 38, 
of electrical pulses or excursions and also necessary to an amplaed replica of the input appears across load re- 
quidrly determine, at a glance, how many of such pulses, sistor 40 (e.g., 2K ohms) connected between the collector 
as z total have occurred. For example, such is the case of transistor 21 and source terminal 34. The output of 
wherein both short time and long time frequency meas- transistor 2% is coup1 acitor 42 (e.g., 10 mf.) 
urernents are being made. 26 to the base input of e.g., 2N244) of squar- 
Previous known existing systems lack versatility, from ing circuit 12. The the input to transistor 
the point of view of operating frequency, and are believed 44, occurring at point A is illustrated as curve A of FIG- 
to mquire an excessive number of components. Accord- 
ing4, an object of this invention is to provide a relative- 
ly wide band indicator of the type described which fea- 30 
tures a substantial reduction in component requirements. 
In accordance with the invention the signal to be ob- 
served, or input signal, is fed to a variable impedance 
mems, such as an electrical squaring circuit, which PrO- necting between ground and the base of transistor 46, c m -  
vides across it a variation in impdance which varies at 35 plete a voltage divider circuit between source plus ter- 
the rate of the input signal but between fixed amplitude minal 34 and ground terminal 36. The output, or load 
limits. This variable impedance means is connected in circuit of squaring circuit 12 is through resistor 54 (e.g., 
series with indicating means such as a recording gal- 2K ohms), resistor 55 (e.g., 330 ohms) and recording 
variometer and a source of current. In this manner each galvanometer 56 interconnecting positive source terminal 
Cycle of the input signal actuates the galvanometer as 40 34 and the collector of transistor 46. Damping or filter- 
square or rectangular current variations occur due to the ing of undesired transient respo 
controlled variations of the impedance means. Voltage itor 57 across galvanometer 56. 
variations which result from this configuration are C ~ U -  regeneratively coupled through 
pled from the variable impdance means to a reSktanCe- 58 (e.g., 500 ohms) connecting the emitters of transistors 
capacitance differentiation circuit which in turn provides 45 44 and 46 to ground terminal 36. 
a spike pulse output to an electrical integrating circuit. 
The electrical integrating circuit provides a narrow width 
voltage output which is proportional in amplitude to the 
number of input pulses which have occurred. This out- 
put is applied to a voltage sensitive impedance means, 50 
such as a unijunction transistor, which abruptly changes 
impdance whenever it is fed a voltage of a certain level. 
This latter impedance means is placed in circuit with the 
indicating means and the variable impedance means de- 
scribed above, and thus changes in current through the 55 
indicating means correspond to both changes, the square 
wave and abrupt variations in impedance to produce a 
dual output from the indicator means. This dual output 
provides an indication af each cycle of the input signal 
and also an indication that a predetermined number of 60 
such cycles have occurred. By appropriate adjustment, 
or selection of the output from the differentiation means, 
this number can be chosen as desired for convenience 
of counting, e.g., every five or ten cycles. 
be apparent from the followhg detailed description when 
considered together with the accompanying drawings in 
whiuh: 
EZGURE 1 is an electrical schematic diagram of an 
iment of the invention; and 
URE 2 i s  a graphical illustration showing a series 
tion d the embod 
The embodiment of the invention shown in FKXJRE 
2, differentiation circuit g4, integra 
emitter circuit of transistor 46 is sufficient to hold transis- 
tor 46 in an "on" condition with the voltage at the collw 
tor of transistor 46 W i g  near ground potential. This, d 
As the amplified input voltage wave-form, illustrated 
in curve A of FIGURE 2, rises in a positive dre&on, 
Ofier objects and features of the present invention will 65 
70 
3,287,840 r 
5 
between galvanometer 56 and ground. Unijunction tran- 
sistor 88 has the characteristic to maintain a relatively 
io high impedance until a critical emitter-base potential is 
reached at which point its base-to-base impeaanince drops 
substantially. Its operation here is such that when the 
potential on capacitor 84, BS illustrated by curve D, 
reaches a critical level there is a very sudden decrease in 
16 resistance in the emitter-base circuit of transistor 88 and 
a spike of current as iUustrated in curve E serves to dis- 
charge capacitor 8%. This also has the effect of pro- 
ducing a sudden surge of current in the base-to-base cir- 
cuit of tran producing a sudden drop h cumnt 
20 through res and ga!vanometer 56. This is illus- 
trated in cu FIGURE 2 showing the total output 
Vidmg output voltage taps at terminals 72 and 741 which registered by galvanometer 96. Here it will be observed 
are selectively contacted by switch 76 to provide an out- that with every fifth cycle there occurs a spike essen- 
put of either voltage .divider termin tially superimposed upon the output shown in curve B, 
7 6  The output of diiferentiation 25 or a composite of the outputs of abrupt impedance chang- 
at terminal 78 and at point C is a se ing circuit 28 and squaring circuit 12. The rate of output 
pulses (wave-form C of FIGURE 2) of an amplitude de- from circuit P8 is, of course, dependent upon the position 
pendent upon whether switch 76 is in contact with ter-- of switch 76 and the values of the resistors of voltage &- 
Iltinal 72: or 74, the higher amplitude being obtainable vide 62. With the values heretofore indicated and with 
when switch 76 is in contact with terminal 72. It is to be 30 switch 76 in circuit with terminal 72, 
noted that the amplitude of the spiked outputs of differ- abrupt impedance changing circuit 1 
entiation circuit 14 are independent of the amplitude of put cycle. In the alternate position 
the input voltage 38 inasmuch as squaring circuit 12 pro- will be an output of circuit 18 every 10 cycles. 
duces an output at point B which is of a constant amp&. Obviously, many modifications and variations of the 
tude. 35 present invention are possible in the light of the above 
Integrating circuit P6, which responds to the output of teachings. It is, therefore, to be understood that within 
differentiation circuit 14, consists basically of transistor the scope of the appended claims the invention may be! 
8@ (e.g. 2N525) which passes a charging pulse of current practiced other than as specifically descnid. 
from terminal 34 through ter resistor 82 (e.g. 68 
ohms) to storage capacitor .g. .5 mf.) connected be- 40 
tween the collector of transistor 80 and mound terminal . . 
and will provide as an output a square wave with Te’egular 
or irregular inputs 3%. 
Circuitry subsequent to squaring circuit 82 generates 
I claim: 
36, in response ta a spike pulse from differentiating circuit 
14. The amplitude of the charging pulse is a function bf . 
the amplitude of the spike pulse applied to the base of 
transistor $0 and is dependent upon whether switch 76 is 4s 
connected to terminal 72 or 74 of differentiating Circuit 
14. With no signd input to transistor 80, the emitter- . 
base bias of transistor 80 is a function of the relative . 
values of the emitter arrd base biasing resistance paths. 
The emitter resistance path is made up d resistor 82 and 50 
the base resistance path consists of either resistor 7@ or re- 
sistor 70 and 68, depending upon the wi t ion  of switch 
In either position, however, the relative paths are 
such that the emitter voltage of transistor 80 is less 
tive than the base of transistor (IO, to hold transist 
in a cutofftondition unless a signal input is applied to 
the base of transistor $0. Resistor 86 (e.g. 390K ohms) 
is of a very high value and provides a small current leak- 
age path across capacitor 8 
The operation of circuit 16 is best illustrated by ex- 00 
amination of curves C and D in FIGURE 2, ,representing 
the voltages appearing at points C and D in FIGURE 1. 
Wave-form C is simply an amplified wave-form of the 
output of differentiating circuit 14 and is a series of spikes 
of an amplitude depending upon the 
input applied to the base of transistor 
tion circuit 24. Wave form D, the potential across ca- 
, illustrates the progressive charging of capacitor 
84 with the application of each current spike C. In 
other words, wave-form D is the integral of wave-form C. 70 
junction transistor $8 (e.g. 2N492) and resistors 98 (e.g. 
39 ahms) and 92 (e.g. 1K ohms) connected in series with 
the base terminals of transistor 88, resistor 
tween an input base t e d n a l  of transistor 8 
Abrupt impedance changing circuit 1 
1. In combination: 
a. a voltage source having first and second terminals: 
b. indicating means connected in series With said source 
terminals for indicating the magnitude of current 
passing through .said indicating means; 
c. first current control means including a first transistor 
connected in series with said indicating means be- 
tween said souice terminals; 
d. an input signal comprising a source of periodic vary- 
ing voltage; 
e. first transistor biasing means responsive to said in- 
put signal and coupled to said first transistor for 
abruptly varying the conduction of said first transistor 
from substantially fully conductive to substantially 
non-conductive once each cycle of said input signal 
so as to cause said first transistor to develop an out- 
put between fixed amplitude limits; 
f. electrical differentiation means comprising a capaci- 
tor and electrical resistance in series having the free 
end of the capacitor coupled to the junction of said 
indicating means and said first transistor and the 
free end of the resistor coupled to one of said voltage 
source terminals for providing a pulse of current for 
each cycle of varying conduction of said first 
transistor; 
g. second current control means including impedance 
means connected in series with said indicating means 
between said source terminals and responsive to an 
electrical input for producing an abrupt change in 
impedance; 
h. integrating control means responsive to the output 
of said differentiation means for providing an elec- 
trical input to said impedance means in response to 
a predetermined number of said pulses from said 
differentiation means. . The combination set forth in claim B wherein said 
3,881,640 
integrating control means comprises a second capacitor 
and switching means coupled to the output of said dif- 
ferentiation means for applying pukes of charging current 
to said second capacitor and including means for provid- 
ing a triggering input from said second capacitor to saki 
impedance means in response to a predetermined number 
of said pulse from said Merentiation means. 
3. The combination set forth in claim 2 wherein said 
switching means comprises a switching transistor and 
emitter load resistor, said second capacitor being con- 
nected between the collector of said switching transistor 
and Said second terminal of saki source, said emitter load 
resistor being connected between the emitter of said 
switching transistor and said first terminal of said source, 
the base terminal of said switching transistor being con- 
nected to an electrical point along said electrical resistance 
of said differential means, and said first terminal of said 
source and said emitter of said switching transistor being 
of like polarity designation. 
4. The combination set forth in claim 3 wherein said 
impedance means is a unijunction transistor and the base 
terminals of said unijunction transistor form the im- 
pedance terminals of said impedance means and the emit- 
ter terminal of said unijunction transistor is connected 
to the CdIector terminal of Said switching transistor. 
I 
a0 
15 
20 
25 
justable value and wherein there are a plurality of elec- 
trical taps at different resistance p in ts  on said electricaf 
resistance, and means for selectively coupling said base 
terminal of said switching transistor to one of said elec- 
trical taps. 
6. The combination set forth in claim 5 wherein sakl 
recording means of said indicating means % a recording 
galvanometer. 
e% 
UNITED STATES PATENTS 
2,873,388 2/1959 Trumbo. 
2,926,984 311960 Oerbrands ------___ 346-62 X 
3,111,591 1111963 Cornon ____-___ 30748.5-21.1 
OTHER REFERENCES 
L. E. Weisner, Transistor Count-Rate Systems, El=- 
trical Engineering, vol. 17, No. 7. July 1958, w. 623-625. 
WALTER L. CARISON, Primary Examiner. 
RUDOLPH 77. ROLDEC, Examiner. 
I. 5. ~~~~~~~, Assisrant Examiner. 


Pulse counting circuit which simultaneously indicates the occurrence of the nth pulse Patent

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