Digital controllers, one using a special-purpose computer and the other using a combination of digital and analog techniques, are designed around /1/ computers that simulate the transfer function and interface with the system, and /2/ analog and digital circuits, converters, amplifiers, constant multipliers, and delay lines that form a digital filter

Carroll, C. C.

Jones, J. W., Jr.

Nagle, H. T., Jr.

English

NASA Technical Reports Server

August 1970	 Brief 70-10314 
NASA TECH BRIEF 
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be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
Two Techniques for Digital Filter .Design 
There are several ways to achieve digital compen-
sation. First, sample-and-hold circuitry may be used 
to generate a compensation transfer function within 
the system; second, general or special-purpose com-
puters may simulate the transfer function and inter-
face with the system; and third, various analog and 
digital circuits, converters, summing amplifiers, con-
stant multipliers, and delay lines may be intercon-
nected to form a digital filter. 
Reports have been made on two generalized third-
order digital controllers designed around the last two 
techniques, one using a special-purpose computer, 
and the other using a combination of digital and 
analog techniques. 
Two mathematical formulations of the transfer 
function of a digital controller exist, called the direct 
form and the canonical form. In both designs, the 
canonical form is used. This form calls for the solu-
tion of the two equations 
m(k) = e 1 (k) - b 1 m(k-l) - b 2 m(k-2) -b3m(k-3) 
and 
e 0(k) = a 0e 1(k) + c 1 m(k-1) + c 2 m(k-2) + c3m(k-3) 
where
c = a - a0 b (j = 1,2,3), a 0 , aj and 
are constants, e 1 (k) is the digitized sample of the in-
put signal, eo(k) is the output signal in digital form, 
and m(k-j) is the time-delayed m(k) of the jth past 
sample. 
In the first design, the special-purpose computer 
is described in four blocks, each of which performs 
specific functions in the solution of the transfer equa-
tion. The first block, input-output equipment, con-
tains a successive approximation-type analog-to-digi-
tal (A/D) converter and a digital-to-analog (D/A) 
converter. The A/D converter provides the input 
signal ei(k) by digitizing samples of the input analog 
waveform e(t). The input voltage is divided into 
2 1 0
 - 1024 distinct magnitude levels, represented by a 
10-bit binary word. The D/A converter restores e0(k) 
into the output analog waveform e 0 (t). Individual 
compensators may require different D/A devices to 
correctly interface with different overall systems. 
The second block, memory, provides the time de-
lay needed for the functions of k-I, k-2, and k-3; 
stores the various constants b 1 , b 2 , a0 , c 1 , etc.; and 
holds the intermediate variables m(k-l), m(k-2), etc. 
Storage of the constants is provided by mechanical 
switches, so that they may be changed easily to modify 
the compensation function. The variables are stored 
in flip-flops in signed-magnitude form. 
The third block, the arithmetic unit, performs the 
various addition and multiplication steps needed to 
solve the two equations. The circuit used consists of a 
parallel binary accumulator logically coupled to two 
shift registers. 
The final block, the control unit, synchronizes the 
operation of the other three blocks. It contains a func-
tion generator to produce the master clock and other 
required timing signals, and also the transfer logic 
circuit, which governs the exchange of quantities be-
tween the memory and arithmetic units. 
The second design is described as a "hybrid digital 
controller," because both analog and digital circuits 
are used. The input analog signal e 1 (t), together with 
three time-delayed intermediate signals, is fed into a 
loop which starts with a summing amplifier. The out-
put of the summing amplifier is coupled through an 
A/D converter, and the digital signal fed through 
three successive buffer registers, producing three 
(continued overleaf) 
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different time-delayed signals m(k-1), m(k-2), and 
m(k-3). These are reconverted to analog signals in 
three separate D/A circuits, fed through phase-
splitting operational amplifiers to allow switch-selec-
tion of the correct arithmetical signs, and through 
three precision resistors to affix the correct value for 
b 1 , b 2 , and b3. These intermediate signals are then 
fed back into the first summing amplifier, closing the 
loop. Thus the loop provides the solution to the first 
equation. 
Outputs are taken from the AID converter (e(k) 
signal) across a phase-splitting operationa.l ampli- 
fier, and also from each of the three delayed signals, 
fed through four precision resistors to attach the 
appropriate value of aj , and then fed through manual 
sign-selecting switches into a second summing ampli-
fier from which the analog output e 0(t), the already 
reconverted solution of the second equation, is taken. 
Thus the combination of digital and analog circuits 
serves to solve the same equations as the special 
purpose digital computer. 
Because of their generality, either of these two 
designs may be easily applied to a wide variety of 
digital compensation applications.
Note: 
Requests for further information may be directed to: 
Technology Utilization Officer 
Marshall Space Flight Center 
Huntsville, Alabama 35812 
Reference: B70-10314 
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C. 20546. 
Source: Chester C. Carroll, Hubert T. Nagle, Jr., 
and James W. Jones, Jr. of 
Auburn University
under contract to
Marshall Space Flight Center 
(MFS-20015 & 20016) 
Brief 70-10314	 Category 01


Two techniques for digital filter design

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