Improved method fabricates electroluminescent planar P-N gallium arsenide diodes. GaAs is masked with silicon monoxide to allow P-type impurities to be diffused into unmasked portions of GaAs to form P-N junctions

Roy, M. M.

Yeh, T. H.

English

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	 P-Type Impurity P-Type Impurity
Junction 
P Material 
GaAs (N-Type) 
.
4 Junction 
GaAs (N-Type) 
(4)	 (5)
	 Top View of Completed Wafer 
August 1969	 Brief 69-10271 
NASA TECH BRIEF	
_G_ 
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3	 ---------.y 
Improved Method of Fabricating Planar Gallium Arsenide Diodes 
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An improved, simple method has been devised for 
fabricating electroluminescent (light-emitting) planar 
•P-N GaAs (gallium arsenide) diodes. The planar-type 
GaAs diode emits substantially equal amounts of light 
from its P and N sides, whereas the light from the P 
side of a common mesa-type GaAs electroluminescent 
diode has approximately half the intensity as the light 
from the N side of a mesa-type diode made by diffus-
ing P-type impurities into the entire surface of the N-
type GaAs wafer to form a P-N junction. The lower 
intensity of light from the P side of such a mesa-type 
GaAs diode is due to the fact that the light absorption 
coefficient of the P-type material is much higher than 
that of the original N-type GaAs. 
Conventional techniques for fabricating other types 
of planar diodes cannot be used in fabricating a planar
GaAs diode. For example, silicon dioxide, which is 
extensively used as a maskant in the fabrication of 
planar silicon diodes and other semiconductive com-
ponents, cannot be thermally grown on GaAs or evapo-
rated onto it at a temperature low enough (below 
about 400°C) to prevent the dissociation of the GaAs. 
In the new method, the GaAs is masked with SiO (sili-
con monoxide) to allow P-type impurities to be diffused 
in unmasked portions of the GaAs to form P-N junc-
tions. The deposition of SiO is performed below the 
dissociation temperature of GaAs. A first step (I) in 
fabricating the planar GaAs diode is to place on the 
GaAs wafer a number of strips of material (e.g., tung-
sten) which do not react with GaAs or SiO. In the 
second step (2), a layer (5000 to 8000 angstroms) of 
SiO is vapor-deposited over the tungsten strips and 
-	 (continued 
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exposed surface of the GaAs wafer. In step (3), the 
tungsten strips with the SiO deposit on them are re-
moved, leaving a series of unmasked openings or slits 
in the SiO deposit on the GaAs wafer. In step (4), P-
type impurity, such as zinc or cadmium, is diffused 
into the GaAs wafer through the slits, forming P-N 
junctions. After the diffusion is completed, the SiO 
mask is etched away, step (5), with an appropriate 
solution (e.g., a hot concentrated solution of hydro-
fluoric acid) and washed with water. The resultant 
wafer may be divided into smaller segments or chips 
to form a number of individual diodes. For example, 
the dotted lines in the top view of the completed 
wafer indicate the division of the wafer into six diodes, 
each with a channel-like diffusion of P material in the 
surface of N-type GaAs.
Note: 
Documentation is available from: 
Clearinghouse for Federal Scientific 
and Technical Information 
Springfield, Virginia 22151 
Price $3.00 
Reference: TSP69- 10271 
Patent status: 
No patent action is contemplated by NASA. 
Source: Tsu-Hsin Yeh and M. M. Roy 
Jet Propulsion Laboratory 
(XNP-04235)
[1 
. 
is 
Brief 69-10271	 .	 Category 01


Improved method of fabricating planar gallium arsenide diodes

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