Implementation of multiplier and accumulator using 8-bit log number system

Abstract

MasterA multiplier and accumulator using a logarithmic number system was proposed to improve floating point hardware by removing hardware multiplier. This new type of multiplier and accumulator was implemented in FPGA by using Verilog code. The multiplier and accumulator in FPGA received 16-bit pcm data from the smartphone and successfully proceeded with multiply and accumulation. The multiplier and accumulator is made up of four blocks; a pcm to log converter, a log decoder, log multiplier, and a kulisch accumulator