Circuit breaker consists of a preset current amplitude sensor, and a lamp-photo-resistor combination in a feedback arrangement which energizes a power switching relay. The ac input power is removed from the load at predetermined current amplitudes

Moore, M. L.

English

NASA Technical Reports Server

chnic Subsystem 
AC Load	 I 
----—J 
Pot 
(Li
September 1970	 Brief 70-10524 
NASA TECH BRIEF 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage commercial 
application. Tech Briefs are available on a subscription basis from the Clearinghouse for Federal Scientific and Technical 
Information, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
Latching Overcurrent Circuit Breaker 
Latching Relay Hill
.	 ..	 I
	 Cl 
Reset
	 (Il 
Signal
	
D2	 Figure 1. Electrical Schematic of
	 Latching Overcurrent Circuit Breaker 
	
Manufacturers of electrical test equipment and
	 Figure 1 illustrates the action of the circuit breaker. 
	
small appliances and personnel concerned with re-
	 A double pole latching relay interrupts both sides 
	
peated nondestructive preflight testing should be 	 of the ac line from the control circuit and ac load to 
	
interested in a latching overcurrent circuit breaker, 	 be controlled. A 3.9 ohm resistor (R I), placed in series 
	
It consists of a preset current amplitude sensor, and
	 with one side of the line, produces a small voltage 
	
a lamp-photo-resistor combination in a feedback
	 drop proportional to the amount of current drawn by 
	
arrangement which energizes a power switching relay. 	 the ac load. A dc voltage to the unijunction transistor 
	
The ac input power is removed from the load at pre- 	 (QI) is supplied by a bridge rectifier. The 15 ohm re-
determined current amplitudes. 	 sistor (R2) provides current limiting and the 47 4 
(continued overleaf) 
	
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of
	 the 
	
Aeronautics and Space Administration. Neither the United States
	
information contained in this document, or warrants that such
	 use 
	
Government nor any person acting on behalf of the United States 	 will be free from privately owned.rights.
https://ntrs.nasa.gov/search.jsp?R=19700000506 2020-03-17T00:33:02+00:00Z
500
I I	 Current-Trip Time 
450 F	 Input Power: 2.4 kHz. 50V. RMS 
Square Wave 
E 
C I
1 
70 
50	
1.0	 2.0	 3.0	 4.0	 5.0	 6.0 
0.3	 TRIP TIME (SECONDS) 
Figure 2. A Plot of Load Current Versus Trip Time 
capacitor (Cl) provides filtering. A 390 ohm resistor 
(R3) supplies temperature compensation for the 
unij unction transistor. The sensor for the circuit is a 
combination light dependent resistor (LDR) and lamp 
assembly. 
As the load current increases, the illumination 
from the lamp increases and lowers the resistance of 
the light dependent resistor. The 2.0 if capacitor 
(C2) charges to the peak point voltage of the unijunc-
tion transistor causing it to fire; this action energizes 
the latching relay which causes the ac power line to 
be disconnected from the load and control circuit. 
Diode (Dl) absorbs the back EMF from the activated 
relay coil. The time constant formed by the 20,000 
ohm resistance (R4) and 2.0 if capacitor determines 
the required trip time. The value of RI determines 
the trip current amplitude. 
Capacitor Cl stores sufficient energy to ensure 
operation of the trip circuit when an overcurrent
surge or transient causes a drop in line voltage. The 
circuit is designed to function reliably for fault 
currents less than 0.5 amp. Once the relay latches, 
which removes ac power from the load and control 
circuit, a pulsed reset signal supplied to the reset 
will place the ac load and control circuit back in 
operation. Diode (D2) absorbs the back EMF from 
the activated reset coil. The reliability and per-
formance of a laboratory test model, upon repeated 
interruption of fault currents less than 0.5 amp, are 
satisfactory. Figure 2 depicts a plot of load currents 
versus trip times for the circuit adjusted to pass a 
steady state current of 150 mA without tripping. 
Notes: 
I. Resistor R in Figure 1 may or may not be required, 
depending on the dark resistance of the LDR and 
the leakage of capacitor C2. 
2. No additional documentation is available. Specific 
questions, however, may be directed to: 
Technology Utilization Officer 
NASA Pasadena Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: B70-10524 
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C. 20546.
Source: M. L. Moore of

Caltech/JPL
under contract to

NASA Pasadena Office
(N PO- lll3l)
S 
Brief 70-10524	 Category 01


Latching overcurrent circuit breaker

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server