Several cycles of photoetching, dopant deposition, and drive-in produce selectively-doped regions and semiconductor junctions within a single chip

Gallagher, R. C.

Williams, D. W.

English

NASA Technical Reports Server

April 1970
	 Brief 70-10218 
NASA TECH BRIEF 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage commercial 
application. Tech Briefs are available on a subscription basis from the Clearinghouse for Federal Scientific and Technical 
Information, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Division. NASA. Code UT, Washington, D.C. 20546. 
Technique for Producing Bipolar and MO  Field Effect

Transistors on a Single Chip 
A method has been described for the simultaneous 
production on a single, monolithic silicon chip of 
vertical npn transistors, lateral pnp transistors, and 
p-channel, enhancement mode MOSFET devices. 
Initially, two epitaxial layers are grown on a p-type 
silicon substrate. The first, p-type, is heavily doped 
with arsenic, and the second, n-type, is heavily doped 
with phosphorus. After the surface layer is oxidized, 
several cycles follow of photoetchi .ng, dopant deposi-
tion, and drive-in, to produce selectively-doped 
regions and semiconductor junctions within the chip. 
In the first cycle, the areas exposed by photoetching 
are heavily doped with boron. These p-type regions, 
together_ with the p-type, arsenic doped epitaxial 
substrate, form channels which isolate each device 
from its neighbors. Second, the base region of the 
npn transistor is doped with boron and driven in 
deeply, to leave space for the emitter. Third, the 
emitter and collector of the lateral pnp transistor, 
and the source and drain of the MOSFET are doped 
with boron. Fourth, the npn emitter and the pnp base 
are doped with phosphorus. 
Next, the gate region of the FET is exposed, the 
device is thoroughly cleaned, and the gate dielectric 
is oxidized. The dielectric is then doped with phos-
phorus, which at the same time forms a phosphorus 
glass passivation layer over the entire chip.. 
Immediately following the doping of the dielectric, 
a layer of aluminum is deposited over the entire chip
by electron beam evaporation. This layer prevents 
shorts-through the dielectric and protects it from 
contamination. 
Contact windows are etched through the aluminum 
and through the underlying oxide, and a second layer 
of aluminum is deposited, filling the contact windows. 
Subsequently, a final etching separates the contact 
regions and forms the bonding pads and intercon-
nections. After sintering to form ohmic contacts, the 
wafers are ready for final evaluation, scribe and dice, 
and packaging. 
Note: 
No additional documentation is available. Specific 
questions, however, may be directed to: 
Technology Utilization Officer 
Manned Spacecraft Center, Code BM7 
Houston, Texas 77058 
Reference: B70-10218 
Patent status: 
No patent action is contemplated by NASA. 
Source: David W. Williams and 
Robert C. Gallagher of 
Westinghouse Electric Corporation 
under contract to 
Manned Spacecraft Center 
(MSC-13358) 
Category 01 
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States	 will be free from privately owned rights.
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Technique for producing bipolar and MOS field effect transistors on a single chip

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