Analog-to-digital converter converts 10 volt full scale input signal into 13 bit digital output. Advantages include high sensitivity, linearity, low quantitizing error, high resistance to mechanical shock and vibration loads, and temporary data storage capabilities

Cox, J.

Finley, W. R.

English

NASA Technical Reports Server

July 1969	 Brief 69-10230 
NASA TECH BRIEF 
NASA Tech Briefs are issued to summarize specific innovations derived from the U.S. space program, 
to encourage their commercial application. Copies are available to the public at 15 cents each 
from the Clearinghouse for Federal Scientific and Technical Information-,Springfield, Virginia 22151. 
Highly Linear, Sensitive Analog-to-Digital Converter 
fl
R 
Input 
Voltage
Ii 
13
Positive Offset 
Voltage 
I4 
Operational 
Amplifier
Strobe
I.'
Accept 
-Comparator
Amplifier 
is
R 
A2R 
2 
-1OV Reference
2R	 1ov=111 -i 
13-- ---------413	 -iov=iii --- o 
]	 LSB =	 = 20V =24414 mV 2n	 213 
The analog-to-digital (A/D) converter shown in the 
schematic was designed to convert a ± 10 volt full 
scale input signal into a 13 bit digital output. The con-
verter has a least significant bit (LSB) weight of 
2.4414 mV and is extremely linear (nonlinearity of 
0.0075 percent of full scale) over the temperature 
range of 00 to 70°C. Other advantages of the converter, 
in addition to its high sensitivity and linearity, are its 
low quantizing error (± 1/2 of the LSB, or ± 1.2207 
mV), its high resistance to mechanical shock and vibra-
tion loads, and its temporary data storage capabilities. 
It has a moderate conversion speed of 20 microsec-
onds per bit, but has been operated equally well at a 10 
microsecond bit rate. 
The A/D converter incorporates a very stable, regu-
lated —10 volt ladder reference supply and a positive
offset voltage supply. The offset voltage effectively 
shifts the ± 10 volt input signal to a 0 volt to +20 
volt input signal at the summing junction of the opera-
tional amplifier. The most significant bit (MSB) of the 
ladder is the sign bit; its current contribution to the 
summing junction is equal in magnitude but opposite 
in sign to that of the offset voltages. Output of the A/D 
converter is in offset binary code corresponding to 
various voltage inputs, as exemplified below: 
Voltage Input
	 Code 
+ 10	 llll ---- ll 
+ LSB	 l000 ---- Ol 
0	 l000----00 
- LSB	 011l ---- lI 
- 10	 0000----00 
As
'(continued overlea) 
MW
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Aeronautics and Space Administration. Neither the United States	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States	 will be free from privately owned rights.
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When a voltage appears at the input terminal, the 
MSB of the ladder is switched from gound to the —10 
volt reference supply. If the sum of the input currdnt 
(I i ) and the offset current (12) is greater than the 
current (1 3 ) furnished by the MSB, the output of the 
operational amplifier goes negative, so that the feed-
back current (1 4 ) will balance the currents at the sum-
ming junction. The output of the comparator, which 
is operated open loop, thus goes positive. At the end of 
the 20 microsecond comparison time, a strobe pulse is 
generated and an "accept" pulse sets a flip-flop to hold 
on the MSB switch. The second bit is then tried. If the 
sum of the input and offset currents is less than the 
sum of the two MSB currents, the second bit will be 
rejected. The cycle continues until all 13 bits have 
been tried and accepted or rejected. The digital data 
are stored in the memory flip-flops which control the 
ladder switches. These data are available for use until 
the flip-flops are cleared prior to another conversion. 
Notes: 
I. The A/D converter was designed for use in a system 
that takes four samples of a measurement parame-
ter. These samples are combined into a ratio form-
ula to cancel the converter gain and offset errors; 
the ratio formula therefore depends only on the 
linearity of the converter. 
2. The first two legs of the 13 bit ladder are external 
to the conventional II bit ladder network. This 
arrangement improves system accuracy by trim-
ming out the error due to voltage drop across the 
switches.
3. The converter employs a gain switch in the feed-
back loop of the operational amplifier. For output 
voltages from this amplifier greater than 0.5 V, 
the gain is unity, which prevents the operational 
amplifier from saturating (thus eliminating the 
time that would be required for it to become un-
saturated). For output voltages less than 0.5 V, 
the gain is 20 to increase the sensitivity of the com-
parator amplifier. 
4. The converter can be temperature-compensated 
to stabilize gain and offset errors. It could then be 
used for absolute voltage measurements to an ac-
curacy of 0.01 percent. 
5. This information is complete in itself. No additional 
documentation is available. 
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C. 20564. 
Source: W. R. Finley and J. Cox of

Gulton Industries, Incorporated

under contract to

Manned Spacecraft Center
(MSC-131 10)
. 
Brief 69-10230	 .	 Category 01


Highly linear, sensitive analog-to-digital converter

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