Decoding tree consisting of 40-bit semiconductor read-only memories interconverts binary and decimal numbers 50 to 100 times faster than current methods. Decimal-to-binary conversion algorithm is based on a divided-by-2 iterative equation, binary-to-decimal conversion algorithm utilizes multiplied-by-2 iterative equation

Lim, R. S.

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December 1970	 Brief 70-10496 
NASA TECH BRIEF 
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application. Tech Briefs are available on a subscription basis from the National Technical Information Service, Springfield, 
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nology Utilization Division, NASA; Code UT, Washington, D.C. 20546. 
Rapid Method for tnterconversio 
The problem: 
To increase the speed of interconversion of binary 
and decimal numbers by avoiding the use of time-con-
suming software subroutines or of slow iterative se-
quential logic circuits.
n of Binary and Decimal Numbers 
which is also the converted binary digit. The decimal 
number digits are represented in the 8-4-2-1 BCD 
form. The dividing-by-2 process is performed on a 
decimal number by shifting, and the shifting is ac-
complished by decoding. The truth table of the 
C1
Decoder Input 
X8 X4 X2 V8
Decoder 
Output 
Y4 Y2 V1 
O 000 0000 
0 001 0001 
0 010 0010 
O 01 1 0011 
0 100 0100 
1 000 01 O 1 
1 001 01 10 
1 01 0 01 1 1 
1 01 1 1000 
1 100 1 1001
Table 1 
The solution: 
The conversion is accomplished by a decoding tree 
consisting of a few 40-bit semiconductor read-only 
memories. The speed of conversion is proportional to 
the propagational delay in the operation of the read-
only memory. 
How it's done: 
The decimal-to-binary conversion algorithm is based 
on the divided-by-2 iterative equation 
Q—1	 j=l2--- n 
i =j—1 
where Q0 = the decimal number N, Q = quotient of 
jth iteration, and b = remainder of jth iteration,
decoder is emulated by a 40-bit read-only memory 
module, and a converter is formed by connecting many 
identical modules in the form of a tree. The tree 
consists of j levels and k columns, where  is the num-
ber of binary digits minus three and k is the number 
of decimal digits. The conversion speed and the num-
ber of modules required for a converter aredependent 
only on j. 
Figure 1 is a decoding tree for converting the 
decimal number (99)10 to the binary number 
(1100011) 2 . The decoding tree implements the divided-
by-2 conversion algorithm; the tree consists of four 
decoders having four inputs CIX8X 4 X, and four 
outputs Y 8 Y 4 Y,Y 1 , with the decoding function mdi-
(eontinued overleaf) 
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Aeronautics and Space Administration. Neither the United States
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https://ntrs.nasa.gov/search.jsp?R=19700000478 2020-03-17T00:29:49+00:00Z
X8
Input 
X4 X2 X1 CO
Output 
Y8
	
''4 "2 
00000 000 
0001 0 001 
00100 010 
0011 0 011 
0100 0 100 
0101 1 000 
01 10 1 001 
01 11 1 010 
1000 1 011 
1001 1	 1 100
Table 2 
Figure 2 
cated in Table 1. The decoder is emulated by a 40-bit 
read-only memory, but the structure of the decoding 
tree grows in complexity such that for any given deci-
mal number having p digits, the number of decoders, 
M db, required for the converter is 
Mdb = 2p(p-1) —(l/2)(4p—n—l)(4p--n) 
where n is the number of digits in the resulting binary 
number. 
The binary-to-decimal conversion algorithm is based 
on the multiplied-by-2 iterative equation 
= 2S n j+I + b 11 j	 j = 1,2, ---, n 
where S = sum of jth iteration, S 11 = b,1-1
 
b1 
-j = binary digit at position n —j, and S 0 is the re-
sultant number in decimal form. Implementation of the 
above equation is accomplished as described pre-
viously. 
Figure 2 is a decoding tree for converting the binary 
number (11111111)2 to the decimal number (255) 10. 
The decoding tree implements the multiplied-by-2 
conversion algorithm. The decoding tree consists 
of seven decoders having four inputs X 8 X4 X,X 1 and 
four outputs C0 Y 8 Y4 Y 7 . The decoding function is 
shown in Table 2. The number of decoders, Mbd,
required for a given converter is
	 (n —4\ 
Mbd = n(p — l) —(3/2)p(p-1) —.TT,11 
where the term (K)/1 as (K) 1 is defined as the integral 
part of K. 
Notes: 
1. With typical commercially available read-only 
memories, the speed of a 15-bit binary-to-decimal 
converter is 540 us and a 4-digit decimal-to-binary 
converter is about 495 ns. Conversion speeds 
are at least 50 to 100 times faster than methods in 
current use. 
2. Since the converter is a combinational net, random 
transient disturbances are without effect and timing 
and clocking are not required. 
3. Additional information is available from: 
Technology Utilization Officer 
Ames Research Center 
Moffett Field, California 94035. 
Reference: TSP70-10496 
Patent status: 
No patent action is contemplated by NASA. 
Source: Raymond S. Lim 
Ames Research Center 
(ARC-10159) 
Brief 70-10496	 Category 09 


Rapid method for interconversion of binary and decimal numbers

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