Module for interconnecting a semiconductor array to external leads or components incorporates a metal external heat sink for cooling the array. Heat sink, extending down from the molded block that supports the array, is immersed in a liquid nitrogen bath which is designed to maintain the desired array temperature

Steward, R. D.

Windsor, H. F.

English

NASA Technical Reports Server

August 1970
	
Brief 70-10378 
NASA TECH BRIEF 
NASA Tech Briefs announce new technology derived from the U .S. space program. They are issued to encourage commercial 
application. Tech Briefs are available on a subscription basis from the Clearinghouse for Federal Scientific and Technical 
Information, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
Coplanar Interconnection Module 
Printed Circuit Board	 InAs Array 
/	 (Top) 
Evaporated Lead 
Exposed Conductors 
Molded Block	 Printed Circuit Board 
\	 / (Side) 
\	 InAs Arra 
Heat 
The problem: 
Operation of most infrared detector elements re-
quires that the semiconductor be cooled well below 
room temperature, frequently to 196eC. In the case 
of an array of elements, it is desirable to use a thin 
film interconnection from each semiconductor wafer 
to external conductors. Existing techniques for such 
interconnection have not provided an adequate heat 
sink for satisfactory operation. 
The solution: 
A module, for interconnecting a semiconductor 
array to external leads or components, which incor-
porates a metal external heat sink for cooling the
array. This heat sink extends downward from the 
molded block that supports the array and is immersed 
in a liquid nitrogen bath which is properly sized and 
vented to maintain the desired array temperature. 
How it's done: 
The semiconductor wafer (InAs array) is bonded 
directly to a metal heat sink by a thermally conductive 
material such as a solder or appropriate metal alloy 
(see fig.). Lead patterns are provided by printed circuit 
boards which allow external connections to be brought 
to a coplanar surface adjacent to the array. The printed 
circuit boards are placed at angles so that the cross 
section of the copper pattern is enlarged. The coplana"r 
surface between the printed circuit leads and the array 
is formed by casting a thermosetting plastic around 
the heat sink and printed circuit boards, thus main-
taining them in proper alignment. Interconnection 
from the array to the printed circuit boards is provided 
by evaporating thin film metal leads across the surface 
of the semiconductor and plastic to the exposed 
printed circuit leads. 
Notes: 
1. This technique has been implemented for 50-el-
ement InAs arrays with satisfactory operation at 
80cC, the normal operating temperature of InAs 
devices. 
2. The following documentation may be obtained 
from:
Clearinghouse for Federal Scientific 
and Technical Information 
Springfield, Virginia 22151 
Single document price $3.00 
(or microfiche $0.65) 
Reference: NASA-CR-86039 (N68-19209), 
Solid State Image Sensor Research 
(continued overleaf) 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19700000364 2020-03-17T00:45:07+00:00Z
Patent status: 
Inquiries about obatining rights for the commercial 
use of this invention may be made to NASA, Code GP, 
Washington, D.C. 20546. 
• Source: R.D. Steward and H.F. Windsor of
General Electric Company 
under contract to
Electronic Research Center 
(ERC- 10237) 
Brief 70-10378	 Category 01


Coplanar interconnection module

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