Three nand gate circuits are used to add error detection and reset logic circuitry for initiating and retaining the correct binary state in the flip-flop circuits of a ring counter. As the input signals are counted, the position of the specified state moves in ordered sequence around circuit loop

Maasberg, W. A.

English

NASA Technical Reports Server

May 1968	 Brief 68-10067 
NASA TECH BRIEF 
n.a 
NASA Tech Briefs are issued to summarize specific innovations derived from the U.S. space program, 
to encourage their commercial application. Copies are available to the public at 15 cents each 
from the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia 22151. 
Self-Correcting, Synchronizing Ring Counter

Using Integrated Circuit Devices 
Output A	 Output B	 Output N 
FIGURE 1. SIMPLIFIED DIAGRAM 
The problem: 
To initiate and retain the correct binary state in the 
flip-flop circuits of a ring counter so as input signals 
are counted, the position of the specified state moves 
in an ordered sequence around the circuit loop. When 
power is turned on, the circuit is likely to be in an 
incorrect state. Error occurs at power-on if any flip-
flops other than the first flip-flop contain an on (i.e., 
using negative true logic, a logical one state). Error 
also occurs during operation if a flip-flop other than 
the specified circuit contains an on or logical one 
state. Conventional monitoring techniques require 
complex circuit configurations and a large number of 
gate circuits to detect an error.
Clock Pulse 
Input 
Output FFA
Output FF B

Output FF N

Nand 1

Nand 2
Nand 3 
(Preset)
to	 ti	 t2	 t3	 t4	 ts 
FIGURE 2. PRESET AND TIMING SIGNAL SEQUENCE OF CIRCUIT

USING NEGATIVE TRUE LOGIC 
The solution: 
Add error detection and reset logic circuitry using 
only three nand gate circuits. 
How it's done: 
Figure I shows conventional ring counter circuitry 
with error detection and reset logic circuitry added 
(in heavy lines). The necessary initial circuit condition 
is to have the output of first integrated circuit flip-
flop (A) in the logical one condition. When this is so, 
a preset pulse P is simultaneously applied to all flip-
flops of the ring counter from nand gate 3 resulting 
in any extraneous logical one's being reset to off (i.e., 
a logical zero state). Thus, the circuit is ready for 
operation, the logical one condition of flip-flop A will 
(continued overleaf) 
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advance to each successive flip-flop in the loop as the 
clock pulse (CP) input signals are counted. 
By adding a single input to the second nand gate (2), 
an external signal may be applied to synchronize the 
ring counter with another external source. 
The CP input is applied to the final gate (3) so 
that the preset pulse P will not last into the following 
clock time and hold the ring counter in the initial 
state. The CP input to the last gate is slightly delayed 
by an RC network; so the flip-flops have time to 
settle before being error-detected. 
Considering the worst possible turn-on circuit 
condition, where output A is a logical zero and 
outputs B and N are logical one's, a signal sequence 
is shown at t0 in Figure 2. Since the flip-flop outputs 
are in these conditions, nand gate 1 output will be in 
the logical one state, because of the redundant logical 
zero input detection, ("1" = B • N), nand gate 2 will 
have--a logical zero output because of the one input 
from nand gate 1, "1" = (NB) A (the same as positive 
logic A + BN). At ti, nand gate 3 will have a logical 
zero output, becapse of the logical one input from 
nand gate 2 and the logical one-going portion of the 
clock pulse ("1" = A + B N • CV). Therefore, a 
preset signal (P) is sent to the flip-flops until nand 
gate 3 returns to one, during the logical zero swing 
of the clock pulse. The preset signal forces output A 
to become logical one and outputs B through N to 
become logical zero's. The preset input is the only part 
of the circuit using positive logic. 
The preset pulse changes each flip-flop circuit from 
the worst-case condition; output A goes to a logical 
one, and outputs B through N go to logical zero's. 
When the clock pulse returns to the logical zero state, 
nand gate 3 returns to a logical one and the preset 
pulse is terminated. Nand gate 2 retains its logical one 
state because of the one input from flip-flop A.
Nandgate 1, no longer sensing logical one's in flip-
flops B through N, changes to a logical zero. Thus, 
normal operation begins with the preset pulse applica-
tion at ti. 
At t2, output A will change to a logical zero and 
output B to the logical one state. Nand gate 2 no 
longer senses a logical one in flip-flop A and returns 
to a logical zero. 
The next count, beginning at 0, the CP and the 
output of flip-flop B causes flip-flop N to set to a 
logical one. Nand gate 1, still sensing a logical one 
from flip-flop N, holds the state preventing any 
change in the preset circuitry. Flip-flop N outputs are 
returned to the inputs of flip-flop A, and in sequence 
with the zero-going CP, at t4, flip-flop N passes the 
one to flip-flop A, accepts the zero in flip-flop B, 
and completes a correct cycle of ring counter opera-
tion. 
A redundant preset pulse will be generated when 
nand gate 2 senses a logical one in flip-flop A. If an 
extraneous logical one were to appear in the ring 
counter for any other reason, either nand gate I or 2 
would have sensed it and caused nand gate 3 to preset 
the counter back to ti condition. 
Note: 
Inquiries concerning this circuit may be di-
rected to:
Technology Utilization Officer 
Marshall Space Flight Center 
Huntsville, Alabama 35812 
Reference: B68-10067 
Patent status: 
No patent action is contemplated by NASA. 
Source: W. A. Maasberg 
of International Business Machines Corporation 
under contract'to 
Marshall Space Flight Center 
(MFS-13901) 
Brief 68-10067	 Category 01


Self-correcting, synchronizing ring counter using integrated circuit devices

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