Phase locked-loop circuit is used for playback motors in digital tape recorders where the reproducer output remains in exact synchronism with an external reference clock over extended periods. It removes the motor dynamics from the control loop so that the loop is stable without damping

Stone, F. A.

English

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June 1966
	
Brief 66-10232 
NASA TECH BRIEF 
NASA Tech Briefs are issued to summarize specific innovations derived from the U. S. space 
program and to encourage their commercial application. Copies are available to the public from 
the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia 22151. 
Electronic Phase-Locked-Loop Speed Control System Is Stable 
The problem: 
To design a stable speed control circuit for playback 
motors used in digital tape recorders where the repro-
ducer output must remain in exact synchronism with 
an external reference clock over extended periods. 
Electromechanical speed control systems which have 
been used for tape recorders are inherently unstable 
and require damping to prevent oscillation. 
The solution: 
A phase-locked-loop circuit that permits phase 
comparison of two signals whose frequency is much 
less than the local oscillator frequency (the local oscil-
lator frequency is divided before its signal reaches the 
phase comparator), and thereby removes the motor 
dynamics from the control loop dynamics, so that the 
loop is stable without damping. 
How it's done: 
A phase error or time displacement between the 
frequency of the sync pulses and the reference clock
input of somewhat less than ± 1/2 bit is permitted, so 
that the reference clock pulses are approximately 1 bit 
wide. These pulses are applied to input 1. The sync 
pulses from the tape are converted to a square wave 
by a one-shot multivibrator and applied to input 2. 
Transistors Q1, Q2, Q3 and Q4 and capacitor Cl 
act as an electronic integrator. Transistors Q5, Q6, 
and Q7 are used to establish the initial condition of the 
integrator. Transistors Q8 and Q9 control the integra-
tion process. At the beginning of the reference clock 
pulse, Q5 is pulsed to turn on Q7. This action initiates 
a large current, I, which produces a rapid rise in the 
integrator output voltage. When this voltage reaches a 
predetermined value, Q6 shuts off Q7. Then as long as 
there are pulses at inputs 1 and 2, the integrator out-
put falls slowly. When either one of the pulses drops to 
zero, 12 ceases to flow and the integrator output holds 
at some intermediate value until the next reset and in-
tegration. If input 1 tends to speed up, the resulting 
integrator output causes the playback motor to slow 
(continued overleaf) 
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Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
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down. If input I tends to slow down, the resulting 
integrator output causes the motor to speed up. The 
tape speed is thus automatically readjusted whenever 
input 1 varies. Since the speed correction is made very 
quickly, the dynamics of a quick response motor do 
not cause instability. The memory feature of the in-
tegrator keeps the tape at constant speed during the 
integration period and permits comparison of very low 
frequency pulses (on the order of 1 cps).
Note: 
Inquiries concerning this invention may be di-
rected to:
Technology Utilization Officer 
Jet Propulsion Laboratory 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: B66-10232 
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C. 20546. 
Source: Frederick A. Stone 
of Raymond Engineering Laboratory, Inc. 
under contract to 
Jet Propulsion Laboratory 
-	 (JPL-SC-084)
S 
Brief 66-10232	 Category 01


Electronic phase-locked-loop speed control system is stable

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