FET comparator circuit detects discrete analog computer output levels without excessively loading the output amplifier of the computer. An FET common source amplifier is coupled by a differential amplifier to a bistable transistor flip-flop. This circuit provides a digital output for analog voltages above or below a predetermined level

Wallace, H. L.

English

NASA Technical Reports Server

V 
May 1966	 Brief 66-10224 
NASA TECH BRIEF 
NASA Tech Briefs are issued to summarize specific innovations derived from the U. S. space 
program and to encourage their commercial application. Copies are available to the public from 
the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia 22151. 
FET Comparator Detects Analog Signal Levels Without Loading Analog Device
The problem: 
To design a voltage comparator circuit capable of 
detecting discrete analog computer output levels with-
out excessively loading the output amplifier of the 
analog computer. The circuit must provide a digital 
output for analog voltages above or below a prede-
termined level. The cost and complexity of the 
circuitry must be lower than those of a conventional 
analog-to-digital converter. 
The solution: 
An FET (field effect transistor) common source 
amplifier to provide high input impedance and 
temperature stability, coupled by a differential ampli-
fier to a bistable transistor flip-flop. 
How it's done: 
The circuit consists of four subsections: an input 
overload protection circuit (CR1 and CR2, with 
coupling isolation resistors, R1—R6); a high input-
impedance amplifier (01 and 02); a differential 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
amplifier (03 and 04); and, a bistable flip-flop (05 
and 06). The circuit is initially aligned by grounding 
the gate of 01 and adjusting R9 until the drain of 
01 approaches —6.6 volts. 01 is pinched off and 02 
is at cutoff. In this condition, CR4 is back biased, 
permitting 03 to conduct through bias resistors R11 
and R12. The voltage drop across R13 back biases 
04 and its collector goes to + 12 volts. This positive-
going signal is coupled through C4 and CR7 and to 
the base of the flip-flop transistor Q6. 06 is turned 
off and 05 is turned on. Thus the T output goes to 
—12 volts and the S output goes to —0.6 volt. This 
is the "logic 1" output condition. 
The gate of 01 sees the voltage difference between 
an applied reference voltage and the analog signal 
input. If the difference between the reference and 
the analog voltages is positive, 01 remains pinched 
off, and the output condition of "logic 1" exists. If 
the difference between these voltages is negative, the 
(continued overleaf) 
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19660000223 2020-03-11T17:32:36+00:00Z
gate voltage causes 01 to conduct, thus allowing 
Q2 to become forward biased. CR4 is forward biased, 
driving the base of 03 negative. Thus 03 is cut off 
and 04 is forward biased. When 03 is cut off, its 
collector goes to +12 volts. A positive-going signal 
is coupled through C2 to CR5 and to the base of 
flip-flop transistor 05. 05 is cut off, and 06 is turned 
on. Thus, output S goes to —12 volts and output T 
goes to —0.6 volt. This is the "logic 0" output 
condition. 
Notes: 
I. This circuit could be used to provide the initial 
circuits for a relay-controlled logic scheme. A 
group of these comparator circuits could be con-
nected to provide a pulse-code-modulated system 
supplying a digital output for sinewave inputs in 
a binary ratio, thus forming a counter.
2. Inquiries concerning this invention may be di-
rected to: 
Technology Utilization Officer 
Marshall Space Flight Center 
Huntsville, Alabama, 35812 
Reference: B66-10224 
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C., 20546. 
Source: H. L. Wallace 
of General Electric Company

under contract to

Marshall Space Flight Center

(M-FS-503) 
Brief 66-10224	 Category 01


FET comparator detects analog signal levels without loading analog device

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