Ripple adder reduces the number of logic circuits required to preform binary addition and subtraction. The adder uses dual input and delayed output flip-flops in one register. The contents of this register are summed with those of a standard register through conventional AND/gates

Cliff, R. A.

Schaefer, D. H.

English

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!SO-36-
Brief 65-10355 
NASA TECH BRIEF 
NASA Tech Briefs are issued by the Technology Utilization Division to summarize specific 
technical innovations derived from the space program. Copies are available to the public from 
the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia, 22151. 
Simple Circuit Performs Binary Addition and Subtraction 
Register A 
Register B 
The problem: To reduce the number of logic cir-
cuits required to perform binary addition and subtrac-
tion. Previous methods have used separate units called 
adders or subtractors and have the disadvantages of 
excessive weight, circuit complexity, and high power 
drain. 
The solution: A ripple adder that uses dual-input 
and delayed-output flip flops in one register. The 
contents of this register are summed with those of a 
standard register through conventiona IAN  gates. 
How it's done: The ripple adding circuit adds the 
contents of registers A and B and places the sum in 
register B. The flip flops that comprise register B
have been modified by the addition of a second input 
trigger and an output pulse delay. 
With a binary "1" stored in a stage of register A, 
the clock pulse passes through the AND gate cor-
responding to that stage and triggers the input of the 
corresponding stage of register B. For addition, regis-
ter B is designed to give an output pulse on the "I"-
to-"0" transition. This output pulse is delayed from 
the input of the next stage to permit the contents of 
register A to be transferred before the ripple pulses 
travel through register B. For subtraction, register B 
is designed to produce an output pulse on the "0"-
to-"l" transition, and the circuit subtracts the con-
tents of register A from the contents of register B. 
(continued overleaf) 
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States 	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States	 will be free from privately owned-rights.
https://ntrs.nasa.gov/search.jsp?R=19650000353 2020-03-11T17:24:51+00:00Z
Notes: 
1. This circuitry may be of interest to manufacturers 
of small computing equipment such as desk-top 
calculators. 
2. Inquiries concerning this invention may be directed 
to:
Technology Utilization Officer 
Goddard Space Flight Center 
Greenbelt, Maryland, 20771 
Reference: B65-10355
Patent status: NASA encourages the immediate 
commercial use of this invention. Inquiries about ob-
taining rights for its commercial use may be made to 
NASA, Code AGP, Washington, D.C., 20546. 
Source: David H. Schaefer and 
Rodger A. Cliff 
(GSFC-399) 
Brief 65-10355
	 Category 01


Simple circuit performs binary addition and subtraction

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