Eight-bit analog-to-digital converter decreases average power consumption and increases component reliability. The converter uses solid-state components in pulse operation and magnetic core components for minimizing power consumption. The magnetic core components also increase reliability

Thornwall, J. C.

English

NASA Technical Reports Server

Analna 
In 
Volt 
Gate 
Pulse 
Input 
June 1965
	
Brief 65-10194 
NASA TECH BRIEF H 
NASA Tech Briefs are issued by the Technology Utilization Division to summarize specific 
technical innovations derived from the space program. Copies are available to the public from 
the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia, 22151. 
Analog-To- Digital Converter Has Increased Reliability and Reduced
Power Consumption
Serial 
Binary 
Output 
The problem: Decreasing average power consump-
tion and increasing component reliability in analog-to-
digital converter circuits. 
The solution: An eight-bit analog-to-digital con-
verter, which uses solid-state components in pulse op-
eration to minimize average power consumption and 
magnetic core components to increase reliability and 
minimize average power consumption. 
How it's done: The input gate pulse allows eight 
400-cps clock pulses to be applied to the memory con-
trol circuit, the sequencer, and the output gate in order
to time and control the formation of the binary num-
ber. The sequencer triggers the reference pulse gener-
ators sequentially from Sg to Si. The output from the 
reference pulse generators is applied to the compar-
ator, where the amplitude of the reference voltage 
pulse is compared to the amplitude of the analog volt-
age input. If the analog voltage amplitude is greater 
than the reference voltage amplitude, there is no com-
parator output, a "1" is formed at the binary output, 
and the memory control circuit triggers that particular 
reference pulse generator for the remainder of the 
eight clock pulses. That particular reference output is 
(continued overleaf) 
NEW
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States Govern-
ment, nor NASA, nor any person acting on behalf of NASA: A. Makes 
any warranty or representation, express or implied, with respect to the 
accuracy, completeness, or usefulness of the information contained in
this document, or that the use of any information, apparatus, method, 
or process disclosed in this document may not infringe privately-owned 
rights; or B. Assumes any liabilities with respect to the use of, or for 
damages resulting from the use of, any information, apparatus, method, 
or process disclosed in this document.
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therefore summed with each of the remaining refer-
ence pulse outputs as they are sequentially triggered by 
succeeding clock pulses (i.e., S8 + S7, S8 + S6, 
S8 + Si). A "0" is formed at the binary output when 
the analog amplitude is less than the reference ampli-
tude and the particular reference generator is not held. 
All of the circuits shown on the diagram are pulse 
type except for the output gate, the comparator, and a 
flip-flop in the sequencer circuit. The memory control 
circuit uses a nonlinear core transformer combined 
with a linear core transformer in a one-shot blocking 
oscillator circuit. The nonlinear core transformer acts 
as the memory element, and the blocking oscillator 
acts as a delay element and places the nonlinear core 
transformer in the proper state of operation. The ref-
erence pulse generators are blocking oscillators using 
nonlinear transformer cores. The sequencer circuit is 
similar to a ring counter, in which a single input pulse 
is transferred from core to core, so that the output of 
each core is used to trigger a reference pulse generator. 
The use of magnetic core components increases relia-
bility both through the inherent reliability of magnetic
core components, and by reducing the number of com-
ponents required. Average power consumption is re-
duced by the use of blocking oscillators, which are in 
a cutoff state part of the time, instead of flip-flops, 
which always have one component conducting. 
Notes: 
I. This invention should be of interest to companies
that manufacture analog-to-digital converters. 
2. Applications of this invention will be limited by its 
rate of operation requiring 200 microseconds to 
form one binary word. 
3. Inquiries concerning this invention may be directed 
to:
Technology Utilization Officer 
Goddard Space Flight Center 
Greenbelt, Maryland, 20771 
Reference: B65-10194 
Patent status: NASA encourages the immediate 
commercial use of this invention. It is owned by 
NASA and inquiries about obtaining royalty-free 
rights for its commercial use may be made to NASA, 
Code AGP, Washington, D.C., 20546. 
Source: Joseph C. Thornwall 
(GSFC-246) 
B65-10194	 Category No. 01


Analog-to-digital converter has increased reliability and reduced power consumption

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