Performance of circuits are compared to determine the optimum circuit configuration for implementation into microelectronic functions. Comparison is made in terms of power drain, propagation time, and component variations with temperature and load

Husson, C.

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June 1965
	 Brief 65-10193 
NASA TECH BRIEF iw 
NASA Tech Briefs are issued by the Technology Utilization Division to summarize specific 
technical innovations derived from the space program. Copies are available to the public from 
the Clearinghouse for Federal Scientific and Technical Information, Springfield, Virginia, 22151. 
Logic Circuit Exhibits Optimum Performance 
The problem: Microelectronic digital circuits are 
available in many forms of logic and are applicable to 
many systems used in telemetry and programing. No 
thorough, comprehensive evaluation of these circuit 
configurations has been made in terms of power drain, 
propagation time, or component variations with tem-
perature and load. 
The solution: To compare the performance of basic 
logic circuits to determine the optimum circuit con-
figuration for implementation into microelectronic 
functions. 
How it's done: Seven basic logic circuits were eval-
uated to determine their performance as NAND and 
NOR gates, universal flip-flops, and applicable cir-
cuits to utilize flip-flops as shift accumulators. The cir-
cuits evaluated were Direct Coupled Transistor Logic
(DCTL), Resistor-Transistor Logic (RTL), Resistor-
Diode-Transistor Logic (RDTL), Emitter Coupled 
Transistor Logic (ECTL), Transistor-Transistor Logic 
(TTL), Diode-Transistor Logic (DTL), and Comple-
mentary RDTL. 
The design constraints imposed on the circuits lim-
ited maximum resistance values to 100,000 ohms, 
power supply voltages to multiples of ±1.35 volts, 
propagation time to less than I microsecond, and rep-
etition rate to 150 kcps. 
On the basis or the test results, complementary 
RDTL offered the best trade-off performance within 
these constraints and state-of-the-art fabrication tech-
nology. This circuit configuration permits NAND and 
NOR functions to be easily fabricated with similar de-
sign and performance characteristics. Switching speeds 
(essist insied us erkul 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States Govern-
ment, nor NASA, nor any person acting on behalf of NASA: A. Makes 
any warranty or representation, express or implied, with respect to the 
accuracy, completeness, or usefulness of the information contained in
this document, or that the use of any information, apparatus, method, 
or process disclosed in this document may not infringe privately-owned 
rights; or B. Assumes any liabilities with respect to the use of, or for 
damages resulting from the use of, any information, apparatus, method, 
or process disclosed in this document.
https://ntrs.nasa.gov/search.jsp?R=19650000191 2020-03-11T17:24:17+00:00Z
are high, and propagation time degrades only slightly
	
2. 
at high temperatures. Noise immunity is good. Fan-
out requirements impose a high, but not prohibitive 
beta requirement. Flip-flop power drain is not exces-
sive. AC set and reset are possible, and shift accumu-
lator features are readily available. 
Notes: 
I. These test results should be of interest to the elec-
tronics industry, specifically to designers and 
manufacturers of integrated digital logic circuits.
Inquiries concerning this innovation may be di-
rected to: 
Technology Utilization Officer 
Langley Research Center 
Langley Station 
Hampton, Virginia, 23365 
Reference: B65-10193 
Patent status: NASA encourages commercial use 
of this innovation. No patent action is contemplated. 
Source: Charles Husson
(Langley- 129) 
Brief 65-10193	 Category No. 01


Logic circuit exhibits optimum performance

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