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Design Feasibility and Prospect of High-Performance Sub-50-nm-Channel Silicon-on-Insulator Single-Gate SOI MOSFET

Abstract

This paper describes advanced results of our evaluation of the minimum channel length (Lmin). For the first time, we have added the constraint of subthreshold swing to that of threshold voltage, which has already been proposed. The Lmin definition that includes the subthreshold swing constraint successfully yields a design guideline for low standby power applications, while the Lmin definition based on the threshold voltage constraint does the same for high-speed applications. In contrast to previous predictions, simulation results indicate that the planar single-gate SOI MOSFET promises better performance, clearing the ITRS roadmap until at least 2007 for low standby power applications.ELECTRICAL AND ELECTRONIC ENGINEERING, 50th anniversary editio

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