Latest Frontier Technology and Design of the ATLAS Calorimeter Trigger Board Dedicated to Jet Identification

Abstract

To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the A Thoroidal LHC ApparatuS (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level-I based on calorimeter data, will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which differ in the physics objects for the trigger selection. The presentation is focused on the jet Feature EXtractor (jFEX) prototype, one of the three Feature Extractors. In few hundreds nanoseconds latency budget, up to 2 TB/s have to be processed to provide jet identification (even large area jets) and measurements of global variables. This requires the use of large Field Programmable Gate Array (FPGA) with the largest Multi Giga Transceiver available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 Multi Giga Transceivers each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signals board. For the 24 layers jFEX board stack-up, the MEGTRON6 material was chosen for its property of low transmission loss with high frequency signals (GHz range) and to further preserve the signal integrity, special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. An integrated test has been installed at the ATLAS test facility to perform numerous tests and measurements with the JFEX prototype