CORE
🇺🇦
make metadata, not war
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Community governance
Advisory Board
Board of supporters
Research network
About
About us
Our mission
Team
Blog
FAQs
Contact us
基于制作离散性对策的高性能CMOS DAC
Authors
于雪峰
石寅
Publication date
1 January 2003
Publisher
Abstract
基于CMOS器件的离散性机理及误差消除对策,研究了高速、高精度嵌入式CMOS数/模转换器(DAC)IP核的设计与实现。采用行、列独立译码的二次中心对称电流源矩阵结构,优化了电流源开关电路结构与开关次序;利用Cadence的Skill语言独立开发电流源矩阵的版图排序和布线方法。在0.6μm N阱CMOS工艺平台下,12-bitDAC的微分线性误差和积分线性误差分别为1LSB和1.5LSB,在采样率为150MHz、工作电源为3.3V时的平均耗为140mW。流片一次成功,主要性能指标满足设计要求
Similar works
Full text
Available Versions
Knowledge Repository of SEMI,CAS
See this paper in CORE
Go to the repository landing page
Download from data provider
oai:ir.semi.ac.cn:172111/17767
Last time updated on 15/03/2019