Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 71-74).State of the art MOSFET performance is limited by the electronic properties of the material that is being used, silicon (Si). In order to continue performance enhancements, different materials are being studied for the extension of Si CMOS. One of the materials of interest, particularly for p-MOSFETs, is Ge because it has very high intrinsic hole mobility. Further improvements in hole mobility can be achieved by straining the material. At the same time it is important to study strained Ge transport in device architectures such as trigate MOSFETs. These devices offer the potential for better scalability than planar MOSFETs via improved electrostatics. The investigation of hole mobility in strained Ge trigate ("nanowire") p- MOSFETs is the focus of this work. To study the effects of strain on Ge as a p-channel material, Strained Germanium Directly on Insulator (SGDOI) substrates were fabricated. The substrates were strained to ~2.4% using lattice mismatch which originates from the growth of Ge on a relaxed Si₀.₆Ge₀.₄ epitaxial layer. A biaxially strained SGDOI substrate was patterned to form Ge nanowires which were measured by Raman spectroscopy to investigate the strain relaxation from the free surface. Another SGDOI substrate was used for nanowire trigate p-MOSFET fabrication. The semiconductor layer structure for the devices consisted of 10 nm-thick strained-Ge with a 5 nm-thick strained-Si cap. On-chip biaxially strained MOSFETs were compared to asymmetrically strained Ge nanowire devices. Significantly improved mobilities (~2x) were observed for nanowire devices with a width of 49 nm compared to the on-chip biaxially strained Ge controls. These mobilities are ~15x over Si universal hole mobility. The impact of strain on the transport of holes in long channel devices is also studied as a function of nanowire width. Mobility decreased for narrower nanowire MOSFETs, likely associated with increased sidewall line edge roughness scattering in narrow lines.by Winston Chern.S.M
