Low latency solution for confidentiality and integrity checking in embedded systems with off-chip memory

Abstract

International audienceThis paper proposes a complete hardware solution for embedded systems that fully protects off-chip memory. Our security core is based on one-time pad (OTP) encryption and a CRC integrity check module. These modules safeguard external memories for embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. The implementation limits memory space overhead to 18.25 or 32.75%. It also reduces memory latency from 22 cycles for an alternate approach to 11 or 3 clock cycles depending on desired performance. The loss for software execution with our solution is only 10% compared with a non-protected solution. A FPGA-based implementation of the security core has been completed to gauge the security overhead and to compare our approach with existing solutions