Timed Functional Modeling for Mixed-Signal Boards inMaintenance Testing: A Case StudyBertrand Gilles, Vale´rie-Anne Nicolas, Laurent Lemarchand, Lionel Marce´To cite this version:Bertrand Gilles, Vale´rie-Anne Nicolas, Laurent Lemarchand, Lionel Marce´. Timed FunctionalModeling for Mixed-Signal Boards in Maintenance Testing: A Case Study. 2006. HAL Id: hal-00607343http://hal.univ-brest.fr/hal-00607343Submitted on 8 Jul 2011HAL is a multi-disciplinary open accessarchive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come fromteaching and research institutions in France orabroad, or from public or private research centers.L’archive ouverte pluridisciplinaire HAL, estdestine´e au de´poˆt et a` la diffusion de documentsscientifiques de niveau recherche, publie´s ou non,e´manant des e´tablissements d’enseignement et derecherche franc¸ais ou e´trangers, des laboratoirespublics ou prive´s.Timed Functional Modeling for Mixed-Signal Boards in Maintenance Testing: ACase StudyBertrand Gilles Vale´rie-Anne Nicolas Laurent Lemarchand Lionel Marce´EA3883 LISYC - De´partement Informatique - Universite´ de Bretagne Occidentale20 avenue Le Gorgeu - CS 93837 - 29238 Brest Cedex 3 Francefgillesjvnicolasjlemarchjmarceg@univ-brest.frAbstractIn the context of maintenance testing and diagnosis offaulty boards, a functional FSM (Finite State Machine)-based model for mixed-signal boards has been introduced[1]. It has been extended for dealing with time sequencesaspects. In this paper, the new modeling technique is pre-sented.1. IntroductionNumerous test methods and techniques have been de-veloped for circuit test [2, 3], associated to the differentstages of product life-cycle, mainly at design and produc-tion levels. Surprisingly, not much interest has been throwninto testing during the maintenance stage. However, main-tenance testing has its own specificity. Thus, our work isrelated to maintenance testing and focus more particularlyon mixed-signal boards.The maintenance stage is one of the step constitutingthe life-cycle of a board. This stage begins after the de-velopment/production cycle. Because of this location inthe life-cycle, this stage is complex. First, the knowledgeabout the board is most often reduced for maintenance peo-ple: no designer direct knowledge, partial documentation,level of confidentiality (military, commercial aspects). Sec-ond, unitary in situ tests are not sufficient because of agedcomponents and their interactions at tolerance limits. More-over, large complexity of boards and safety aspects in em-bedded systems (avionics, automotive,...) have to be man-aged. All of this implies functional testing in order to checkthe board behavior, and to determine and replace faultycomponents in case of defective functionality. Since theyonly make use of the external behavior of the components,functional-based models may address a wide spectrum ofsituations concerning board maintenance testing: they maybe adapted to the amount of information available (compo-nent specification levels), to the nature of the components(digital, mixed-signal, or analog) and to the goal of the test(go-nogo, fine-grain diagnosis oriented testing). Functionaltesting of component is not used during design or produc-tion stages because test software development is costly. Itis mainly achieved at the system level in order to test theinteractions between components and to check if the globalsystem meets its specification requirements. Thus, there isno predefined functional tests available at the board level.Moreover, because of lack of material, diagnosis andrepair is often realized in an empirical way. Clearly,specialized tools are needed to guide or automate at leasta part of the work involved in the maintenance stage. Ourgoal is to provide a help to board maintenance testingand diagnosis. We propose a method supported by asemi-automatic tool allowing the functional specificationof the board, the definition of testing strategies and theautomatic test data set generation. Because automationimplies using formalism, the formalism has to be chosento match background practitioners in order to be reallyuseful. Talking with our industrial partner, we chose theFSM formalism which is well known by testing engineers.We first present the FSM-based functional model formixed-signal boards. New time modeling features are de-scribed next. Then, the model-based ATPG (Automatic TestPattern Generation) is presented and we deal with a simplecase study. Then, we show the implementation prototype.A discussion on future work ends the paper.2. FSM-based board modelingA board modeling for maintenance ATPG has been pro-posed in [1]. It relies on FSM-based functional models forthe components of mixed-signal boards.s1m1m2s2b3b2b5b4b1Figure 1. A board is an assembly of blocks.2.1. Board level modelingThe board is first modeled at the board level, as a set ofinterconnected functional blocks, as depicted in picture 1.In addition to building blocks of the board, some externalblocks are needed to model connections between the boardprimary inputs/outputs (PI/PO) and an automatic test equip-ment (ATE): external sources which supply input signals, oroutput measurement points.Blocks are analog, digital or mixed-signal, and may haveseveral inputs and outputs. Oriented links denote data ex-changes between components. Signals exchanged on a linkare characterized by their amplitude, form, frequency andtype.FSMtest model test vectorssequencesbased ATPGprogrammingconstraint logictest strategyFSMFSMfunctional modelFigure 2. The test pattern generation pro-cess.The board checking consists in testing each block indi-vidually using its associated FSM-based test model. Thistest model is created by merging a block functional modeland a testing strategy, as depicted in picture 2. Test vectorsfor a component are generated by covering each transitionof the component’s test model. Since the block under testis often embedded within the board, without any test accessmechanism (e.g. block b3 of picture 1), the functional mod-els of adjacent components are used for justification andpropagation of the block I/O up to PI/PO. Final vectors arecomputed using constraint logic programming (CLP).2.2. Blok level modelingThe proposed approach for the functional modeling ofthe components is based on communicating FSM, sincethese objects are flexible enough to handle various kindsof board specifications.The functional model of each component is a set of com-municating FSM. The FSM model may be specified with anappropriate graphical user interface (GUI), derivated fromsome VHDL/AMS subset specification, or instantiated froma parametrized functions library. The latter is mainly usedfor common analog or mixed-signal blocks. Test vectorslists are also usable. Sometimes, these are the simplest wayfor specifying blackbox-like blocks functionalities.All of these specification techniques may be mixed, ac-cording to the nature of the system components, and to thekind and form of available descriptions for the differentblocks.The test model To generate appropriate test vectors for agiven component, testing strategies are applied to the func-tional model [4]. This is realized mainly by extending thefunctional model FSM at I/O points, with new FSM piecesimplementing the testing strategy. The test model for a com-ponent results from this merging. Since test patterns genera-tion corresponds to FSM transitions covering, strategies aredescribed as combinations of transitions. As a simplistic ex-ample, checking one digital output pin activity correspondsto some test vectors with 1 and some others with 0 for thispin. These vectors are generated from a FSM containingtransitions for both the 0-value and the 1-value.2.3. Time aspetsFrom experimented test engineers point of view, it ap-pears that, for at least go-nogo testing, simple time man-agement is often sufficient. In the context of maintenancetesting, the modeling of accurate delay values is not neces-sary. These values are often either useless, or unavailable.The former arises when approximative clock frequency isset by engineer for test run, the latter when the board comeswithout timing information. However, at least sequences ofvalues are necessary for meeting test requirements. Thus,ordering test data is mandatory. Since the model presentedin [1] is based on communicating FSM, it is of interest tomodel time with such objects.Our first approach to deal with time sequences is basedon a simple clock model. Its FSM is similar to a board inputmodel as time may be considered as an external data for theboard. Multiple clocks may coexist in the same functionalmodel. The different actions driven by a clock are speci-fied by waiting for the top value on some transition of thereceiving FSM. In our modeling, a behavior of the board isrepresented by a path from PI to PO in a set of communicat-ing FSM. Thus, sensitizing a path leads to cross the clocksedges a number of times and thus to compute dates in termsof number of tops for the associated test data.With this kind of modeling for clocks, time modeling isdecoupled from the component modeling. Clock modelsmay be generated automatically and changed easily accord-ing to testing needs without modifying the remaining partsof the model.However, this time management may not be sufficientin some cases. Suppose a modeling with two clocks Clk1andClk2sending top1and top2respectively. These tops donot have an associated date (time stamp). The test patterngeneration process explained in section 2.4 ”asks” for sometop events in order to obtain a test data for a component.This test data is a sequence dated in a relative way. Thus,the real dating of the test data comes from the ordering ofthe top events. If there is no constraint on the periodicityof the two clocks, a consistent timing may be associated tothe test data. Otherwise, a generated test data may have awrong timing because the sequence of top events may beconflicting with the period of each type of event.A first approach to solve this problem is to increase thealgorithmic complexity of the generation process in order toeliminate wrong sequences. An alternative approach con-sists in using time stamped events with a same time refer-ence. Thus, the test data is dated in an absolute way. Wechoose the second approach in order to control the algorith-mic complexity. Thus, we propose to manage time stampedevents. This is achieved by using timed automata [5]. In-deed, timed automata allow to specify time-dependant be-haviors with clocks (like periods) using the same time ref-erence. This approach is illustrated on the case study (seesection 3).2.4. Model-based ATPGAs explained in section 2.1, ATPG is achieved by cover-ing the test models. Covering a transition leads to meet theassociated data constraints. The constraints are propagatedup to the board’s PI/PO, also modeled as FSM. The problemof test data generation is faced using CLP and classical al-gorithms for finite state machines (transition coverage, statecoverage, path coverage). Thanks to CLP, test data are rep-resented in a symbolic way, using ranges of values, dealingefficiently with analog and digital data representations in anuniform way.Ranges of vectors are computed for reaching the test re-quirements. Actual values are defined at the end, makingpossible to take into account some ATE specificities.3. Case study: The tachy boardThe modeling technique, extended for dealing with timesequences aspects (see section 2.3) has been applied to asimple industrial case study. We first give a functional de-scription of the Tachy board. Then, we present the boardmodeling, the testing strategies applied and finally give theexpected board testing results.3.1. Board DesriptionThe Tachy board is a mixed-signal board. It has fourteenanalog channels receiving DC signals coming from tachy-metric generators. The main function of the board is tocheck in a cyclic way the values of input signals by com-paring them to two voltage thresholds and write into RAMmemory the time stamped number of each faulty channel. Achannel is faulty if its analog signal is not between the twothresholds. The RAM memory is reseted every six minutes.For sake of simplicity, we are presenting in the papera three channels restricted version. This restriction has noincidence on the complexity of modeling and testing.3.2. Board ModelingMP2MP3S1S2S3C1C2C3DMem1Mem2Mem3MP1MP2MP3Clk ResetFigure 3. The Tachy board level modeling.Figure 3 shows the Tachy board level modeling (seesection 2.1). The board is delimited by the dashed rectangleand is made of three mixed-signal blocks C1 C3, onedigital block D and three digital blocks Mem1 Mem3.Ciis a two-level comparator, D is the controller whichchecks cyclicly the comparators outputs and Memiisa memory (register). Blocks S1 S3represent analogsources and block MP1 MP3represent digital mea-surement points. Block Clk represents a clock signal andblock Reset represents a reset command.Each component has to be described at the block level(see section 2.2). We now present the functional modelsof the different blocks of the Tachy board. Blocks interac-tions are embedded in blocks descriptions. We begin withthe modeling of the board inputs/outputs, next the modelingof the mixed-signal part (comparators blocks), and finallythe modeling of the digital part (controller and memory).Specification of accurate testing strategies and resulting testmodels are discussed last.Since we make intensive use of communicating FSM, weexplain this aspect first.Communicating FSM The block set of the board corre-sponds to a set of communicating FSM. Since communica-tions are involved, FSM transitions are decorated with la-bels of the form S ! G[A℄ where S is an optional synchro-nization condition between FSM, G an optional booleanguard and A an optional action. The associated seman-tics is: ”when the synchronization condition is verified, theboolean guard is then evaluated. If the guard is true, thetransition is being crossed and the action is done”.The synchronization condition S may be a list of the ex-pression F ? (d1; d2; : : :) which means a blocking receivingof didata list from FSM F .The communication between two FSM is realized witha queue. Sendings are allowed in actions as there are notblocking. F ! (d1; d2; : : :) means a not blocking sending ofdidata list towards FSM F .Board inputs/outputs The modeling of data I/O (boardinputs/outputs) is particular. Data are not functional blocksof the board. However, to generate test data, we need tomodel them. This also allows to model characteristics ofsources, generators and measurement tools of a specificATE in order to produce a test program. Thus, each boardinput/output has a functional model (but no test model as itdoes not correspond to a board component).Figure 4 presents the functional model of the analog Sisource. FSM Si(by convention, FSM name is the same asblock name) sends the x data (which characterises the sig-nal) to FSM Ci. The Tachy board inputs (S1 S3) are mod-eled by three instances of this source.MP2MP3S[Ci!x℄Figure 4. The functional model for a sourceSi.Figure 5 (a) shows the functional model of the clock sig-nal. FSM Clk sends a time stamped top event to FSM D.This behaviour is achieved using the y reference clock.Figure 5 (b) shows the functional model of the reset sig-nal. FSM Rst sends periodically (with a T1= 6mn period)a time stamped reset event to each FSM Memi, using thesame y reference clock and a constraint where % representsthe modulo operator.Concerning outputs modeling, figure 6 shows the func-tional model of a measurement point MPi. FSM MPijustwaits for data coming from FSM Memior FSM D.Mixed-signal part The mixed-signal part of the board ismodeled by three instances (C1 C3) of one communicat-ing FSM.MP2MP3Clk[D ! top(y)℄Rst(y%T1== 0)[8iMemi! reset(y)℄(a) (b)Figure 5. The functional model for the clocksignal and the reset signal.MP2MP3MPMemi? (x; z)D ? zFigure 6. The functional model for the a sim-ple measurement point MPi.Figure 7 presents the functional model of the Cicom-parator. FSM Ciwaits for the x data coming from FSMSi. Two different behaviors may occur when the x data isreceived: Cisends the digital value 1 to FSM D if the re-ceived value does not fall within the expected voltage range,the digital value 0 is sent to FSM D otherwise.Due to the physical characteristics of a comparator, a tol-erance Æ is introduced to ensure that the comparator willhave a good response. This tolerance is expressed in thresh-old percent.MP2MP3DAKOOKSi?x!x(1Æ)Si?x!x(2+Æ)D!1Si ?x!x(1+Æ)&&x(2Æ)D!0Figure 7. The functional model for a compara-tor Ci.Digital part The digital part of the board is modeled byfour communicating FSM: one modeling the digital con-troller of the board and one for each three memories. We ex-plain first the modeling of the controller and next the mod-eling of memory.Figure 8 shows the functional model of the D controller.When a time stamped top event is received from FSM Clk,output data sent by a comparator Ciis read and checked.If the input signal of the comparator is faulty, then a timestamped error flag (which is equal to one) is sent to FSMMemiand D waits for the next top. Otherwise, for testingneeds, the time stamp of the top is sent to FSM MPiandD waits for the next top. As we may see, FSM D checksin a cyclic way the output of each comparator, starting withthe comparator C1(start state). FSM D ensures that a com-parator output is always read between two tops.MP2MP3CC1CC2CC3Clk?top(z); C1?x! x == 1[a℄Clk?top(z); C1?x! x == 0[b℄Clk?top(z);C2?x!x==1[a℄Clk?top(z);C2?x!x==0[b℄Clk?top(z);C3?x!x==1[a℄Clk?top(z);C3?x!x==0[b℄R ? reset(z)! [8iMemi! reset(z)℄R ? reset(z)! [8iMemi! reset(z)℄R ? reset(z)! [8iMemi! reset(z)℄Figure 8. The functional model for the con-troller D with a =Memi!(1; z) and b =MPi!z.The functional model of a memory Memiis depictedin figure 9. FSM Memiwaits either for a time stampeddata from FSM D or for a time stamped reset event comingfrom FSM Rst. The former sends the received data (thetime stamped output value of the Cicomparator) to FSMMPi. The latter sends a time stamped zero-value (becauseof the reset event) to FSM MPi.MP2MP3MemD ? (x; z)! [MPi! (x; z)℄Rst ? reset(z)! [MPi! (0; z)℄Figure 9. The functional model for a memoryMemi.3.3. Testing strategies and test modelsThe default test model for the controller D is the sameas its functional model because it is a digital component.This is also true for all the memories Memi. Indeed, a dig-ital component is easily modeled with a FSM and in ourmethod, the transition covering of this FSM is often suffi-cient for testing the component. When the digital defaulttest model is not sufficient, we apply testing strategies tothe outputs (measurement points).The comparator component is implemented in our li-brary of analog components. Thus, is has an associated de-fault test model depicted in figure 10. It shows that four testdata are required for the unitary test.As previously mentioned, block testing strategies maybe specified by the user to improve testing process. It rep-resents the testing engineer skills. A component test modelis obtained by merging the block functional model and itseventual associated testing strategy.An example of testing strategy applied to measurementpoints is shown in figure 11: we have to check the dating ofat least one error flag for each channel as well as the datingof at least one reset event and the dating of at least one gooddata on at least one channel.MP2MP3DAKOOKSi?x!x==(1Æ)Si?x!x==(2+Æ)D!1Si ?x!x==(1+Æ)Si ?x!x==(2Æ)D!0Figure 10. The test model for a comparatorCi.3.4. Board TestingThe test data set of the board generated with our methodis: TDS = fTD1; TD2; TD3; TD4; TD5g with:TD1= (In = ((11 Æ; ?; ?; top(z1); );(?; 12 Æ; ?; top(z2); );(?; ?; 13 Æ; top(z3); ));Out = (([1; z1℄; ?; ?); ([1; z1℄; [1; z2℄; ?);([1; z1℄; [1; z2℄; [1; z3℄)))with 8k: 6k =2 [z1; z3℄ and z1< z2< z3PSfrag replacementsMP2MP3MPMemi? (x; z)! x == 1 [hek z℄Memi? (x; z)! x == 0 [hek z℄D ? z [hek z℄Figure 11. The test model for a measurementpoint Memi(functional model with an addedtesting strategy).TD2is like TD1replacing 1i Æ by 2i+ Æ.TD3= (In = (?; ?; ?; ; reset(z));Out = ([0; z℄; [0; z℄; [0; z℄))with 9k: z = 6kTD4= (In = ((11+ Æ; ?; ?; top(z1); );(?; 12+ Æ; ?; top(z2); );(?; ?; 13+ Æ; top(z3); ));Out = (([?; z1℄; ?; ?); ([?; z1℄; [?; z2℄; ?);([?; z1℄; [?; z2℄; [?; z3℄)))with 8k: 6k =2 [z1; z3℄ and z1< z2< z3TD5is like TD4replacing 1i+ Æ by 2i Æ.An input 5-tuple has the form (S1; S2; S3; Clk;Rst) andan output 3-tuple has the form (MP1;MP2;MP3) whereS1, S2, S3are the three analog sources, Clk the clock sig-nal, Rst the reset command, and MP1, MP2, MP3thethree digital measurement points (memory state).? stands for an unspecified value and stands for noinput value. 1iand 2iare the thresholds of a comparatorCi(associated with source Si).TD1means that 3 input test vectors are executed sequen-tially on the board, and that 3 corresponding output vectorsare then observed.First test vector puts the event top at time z1on the clockinput, 11 Æ on the S1input, no event on the reset input,and whatever values on S2and S3. Results observed arevalue 1 with time-stamp z1on MP1output, values on MP2and MP3outputs don’t matter.Then, second test vector puts the event top at time z2onthe clock input, 12Æ on the S2input, no event on the resetinput, and whatever values on S1and S3. Results observedare value 1 with time-stamp z1still on MP1output, value 1with time-stamp z2on MP2output, value on MP3outputdoesn’t matter.Next, third test vector puts the event top at time z3on the clock input, 13 Æ on the S3input, no eventon the reset input, and whatever values on S1and S2.Results observed are value 1 with time-stamp z1still onMP1output, value 1 with time-stamp z2still on MP2output and value 1 with time-stamp z3on MP3output.Time-stamps z1; z2and z3must match the constraint:8k:6k =2 [z1; z3℄ and z1< z2< z3.TD1and TD2test faulty behaviors (thresholds exceed-ing for all channels). TD4and TD5test good behaviors(for all channels). TD3test the reset command.We thus consider that this test data set is sufficientto test the board. The size of each test data of TDS isminimal, but we could have generated fewer test data witha bigger size. Note that the generalisation to the wholeboard is immediate: for fourteen channels, the size ofthe test data set is the same (5), but each test data exceptTD3corresponds then to sequences of 14 (instead of 3)input/output vectors of size 16 (instead of 5), and TD3isthe same with input/output vectors of size 16 (instead of 5).However, TD4and TD5may seem meaningless as theysucceed whatever their output values. This is because thereis no writing in memory for good input values, and thusmemory keeps its initial state, which is not defined in TD4and TD5. One improvement may be to sequence TD3be-fore TD4and TD5to fix an initial memory state.The resulting test data set of the board would then be:TDS0= fTD1; TD2; TD34; TD35g with TD1and TD2as previously defined andTD34= (In = (?; ?; ?; ; reset(z));(11+ Æ; ?; ?; top(z1); );(?; 12+ Æ; ?; top(z2); );(?; ?; 13+ Æ; top(z3); ));Out = (([0; z℄; [0; z℄; [0; z℄);([0; z1℄; [0; z℄; [0; z℄);([0; z1℄; [0; z2℄; [0; z℄);([0; z1℄; [0; z2℄; [0; z3℄)))with 9k1: z = 6k1with 8k: 6k =2 [z1; z3℄ and z < z1< z2< z3TD35is like TD34replacing 1i+ Æ by 2i Æ.4. PrototypeWe have partially implemented the FSM-based boardmodeling, the model-based ATPG and time management ina prototype tool. This prototype provides a GUI allowinghigh level description of mixed-signal boards. In addition,the GUI includes some facilities for the choice of a testingstrategy, for the description of the board-ATE connectionand for the description of the data (signals) flow. The GUIpart of the prototype is written in C++ with the ILOG Viewsgraphic library [6] and the ATPG part is implemented usingCLP with the solver ECLiPSe [7]. The prototype, whichis still under development, has already been used in simpleindustrial case studies [1, 4].5. Conclusion and future workWe have presented a method for the testing of mixed-signal boards in a maintenance context. An approach us-ing timed automata has been proposed to deal with simpletime aspects. In particular, it allows the modeling and test-ing in presence of multiple clocks (dependant or not) withdifferent periods. The method has been validated on twosimple industrial case studies. Nevertheless, we are alsoprospecting for improved testing strategies. Another objec-tive is to extend the models to take into account more com-plex boards. Further work is required on industrial cases tovalidate the approach and exhibit its limits.AcknowledgementsWe wish to acknowledge the support provided by theBrittany Regional Council (France) under contract number20041592, and Bruno Castel and Michel Le Goff from ISIS-MPP for their contribution to this project.References[1] B. Gilles, V.-A. Nicolas, L. Lemarchand, L. Marce´, andB. Castel. Towards a New Modelling of Mixed-SignalBoards For Maintenance Testing. In Proceedings of the11th IEEE International Mixed-Signals Testing Work-shop, IMSTW’05, pages 90–97, June 2005.[2] Mark Burns and Gordon W. Roberts. An Introductionto Mixed-Signal IC Test and Measurement. The OxfordSeries in Electrical and Computer Engineering. OxfordUniversity Press, 2001.[3] M. L. Bushnell and V. D. Agrawal. Essentials of Elec-tronic Testing for Digital, Memory and Mixed-SignalVLSI Circuits. Springer, 2000.[4] V.-A. Nicolas, B. Gilles, L. Lemarchand, L. Marce´, andB. Castel. A Maintenance-Oriented Board Testing Ap-proach. In Proceedings of the 3rd IEEE InternationalEast-West Design and Test Workshop, EWDTW’05,pages 143–147, September 2005.[5] Rajeev Alur and David L. Dill. A theory of timed au-tomata. Theoretical Computer Science, 126(2):183–235, 1994.[6] ILOG. ILOG Views Fundation 5.0 User’s Manual,2002.[7] A. M. Cheadle, W. Harvey, A.J. Sadler, J. Schimpf,K. Shen, and M.G. Wallace. Eclipse: An Introduction.Technical Report IC-Parc-03-1, IC-Parc, Imperial Col-lege London, 2003.

Timed Functional Modeling for Mixed-Signal Boards in Maintenance Testing: A Case Study

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