Sollman, G. H.

Weng, L. J.

English

NASA Technical Reports Server

"Variable Redundancy Product Codes" 
L. J. Weng and G. H. Sollman 
Northeastern University 
Bo st on, Massachusetts 
ABSTRACT 
(This paper is  intended for  the Communication Technology Group, (1) Session 4: 
Space Communications, (2) Session 9: Data Communications - The 1967 View, 
and (3) Session 8: Advances i n  DQta Cormrmnications, Telegraph Systems, and 
Facsimile. ) 
- - " I - - Y - c I - - - - - " - - - - - ~ ~ ~ ~ - - - - - - - - L " - - - - ~ - - - - " - - - - - - - ~ ~ ~ - - - - - - - - - - - - ~ - ~ - " - " - ~  
The tensor product codes, as either i terated codes or error-locating codes, 
possess the property of variable redundancy (allowing up t o  eight different levels 
of error control). 
codes can be decomposed into the implementation of the component codes. The 
selection of eight encoder modes yields four i terated codes and four error-locating 
codes that  lend themselves t o  both adaptive coding and feedback transmission 
strategies e 
It i s  shown that the implementation of an encoder for  such 
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"Variable Redundancy Product Codes"* 
L. J. Weng and G. He SolLmrrn 
Northeastern University 
Boston, Massachusetts 
moPsIs 
The concept of iterated codes has been under discussion for more than a 
decadeel It was pointed aut by Slepian* that the generator matrix of an iterated 
code can be expressed as the tensor product of the (two) generator matrices of i ts  
component codes. Becently the idea of an error-locating code3 has been developed 
and its parity-check mtrix w a s  t o  be the tensor product of the parity-check 
matrices of its component codes. $ 5 9  A t  t h e  sane t i m e ,  Tang7 has proposed a single 
encoder which may be used t o  encode dual, cyclic codes (thereby providing two encoder 
modes of different redundancy). These ideas have been drawn upon t o  develop an 
eight mode encoder whose code words are of constant trord block length and offer 
eight levels of redundancy. This coding technique is particularly suitable for 
channels w2th v m n g  characteristics due t o  such factors as weather conditions, 
interference from adjacent channels varying transmission tiis tance (especially 
fn the case of space commmicationsj, etc. 
product code into the implementation of i t s  camponent codes, and (2) t o  present 
a single encoder which wl l l  encode information according t o  any of eight dual 
product codes, and t6ereby yielding a wide range of error-control capabilities 
providedthe coinponent codes are cyclic. 
The purpose of this paper i s  (I) t o  decompose the implementation of the - 
. 
It has been shown Q that  a systemtic (n,k) cyclic code with generator polynomial 
h(x) = 1 + hlx + h p  + ... += hk_I$-l + xk, where the coefficients 
either 1 or 0, can be generated by either of the encoders given i n  
*This work was  performed under the joint support of Air Force 
Iztboratories under Contract No. ~~19(628)-3312 and ERC, NASA Grant 
g i  €I.t-ld hi are 
Fig. 1 or Fig. 2. 
Cambridge Resemh 
NO. NGR-22-011-013. 
Mod. 2 Adder 
(NOTE: - In  binary the multiplier i s  either 0 or 1, w i t h  the mR0 denoting 
no connection and ONE denoting a completed connection.) 
S is at position lwhen information digi ts  are incoming, then switches 
to posLtion 2 t o  receive checking digits. 
when S is i n  position 2. 
Switch K i s  closed only 
Fig. 1 Encoding (n,k) Cyclic Code by Polynomial g(x) 
Code Words 
Switch S i s  at position lwhen information d ig i t s  are incmlng, 
then switches t o  position 2 f o r  the checking digits. 
K i s  closed onlywhen S is i n  position 1. 
Switch 
Mg. 2 Encoding (n,k) Cyclic Code by Polynomial h(x) 
-2- 
With the exception of the input mtput connections and switch timing, the 
encoders of Fig. 1 and 2 are seen to  be identical. 
exploited t o  encode dual cyclic codes by a single encoder.7 
It is th i s  fact  which is 
Iterated Codes 
codes.8 Here we i l lus t ra te  only the encoding circuits for  the product codes 
whichmay be easily converted f r o m  one code t o  the other. 
concept o f t h e  encoder i s  t o  consider the tensor product as gating the second 
camponent code by the first one. 
component matrices, G1 and G2, of (nl, kl) sad (np, k2) codes, respectively: 
&ere axe several ways t o  implement the iterated codes and error-locating 
The fundamental 
kt the generator matrix Gg of an iterated code be the product of two 
G = G1@* = e . . 0 . 
e e e 1 
e . . . . e 
Each row vector of the mat* G is  of the form 
where a*(*) is a row vector of G2. A code word of the iterated code i s  a linear 
cambin- of these vectors. 
as sham i n  Fig. 3. 
into the sub-encoder for  the second component code. 
Hence the encoder for  the iterated code follows 
The information i n  groups of % digi ts  each i s  fed sequentially 
The sub-encoder may be designed according t o  either Fig. 1 or Fig. 2 as desired. 
Every subblock of % digits of the output of the sub-encoder i s  fed into 
However, one configuration will a l w a y s  require fewer delay elements and modulo two 
adders. 
a buffer storage, for  a total of kL subblocks. 
elements i n  the columns of the first component code generator matrix 
( a u ( l )  a p i ( l )  
nl, nl-l, n1-2,...,1. 
fromthe buffer storage. 
the checking digits. 
The gates are controlled by the 
akli (l))T and the order of i is frm right t o  le f t ,  Le. ,  
Each value of i controls the gating of a group of 9 digi ts  
The outputs of the gates are summed, modulo two, t o  form 
-3- 
Information Digits . Check Digits 
L-rl 
U 
Information Digits Code Words 
( i w J 4  (outpue) 
Switch S i s  in position 1 fo r  incoming information digits, and then 
is moved t o  position 2 f o r t h e  checking digits. 
Mg. 3 Encoder f o r  an Iterated Code 
-4- 
The controlling elements a l i ( l )  J 0 . . Jak i (1)  can be easi ly  generiteti by a 
The input/output connections and t i m i n g  
Alternatively, the controlling element generator can be altered t o  
1 sequence generator c o k c t e d  according t o  gl(x) J the generator polynomi~ll of the 
first component code. 
be operated i n  four different modes. 
of the sub-encoder can be changed (by employing suitable switching) t o  those of 
its du.?.l.. 
genera'ee sequences according t o  hl(x)J the recursive polynomial of the first , 
component code. 
Also, it should be noted that the encoder of Fig. 3 can 
,. 
Error-Locat ing Codes 
those of' two bomponent codes, El and %: 
L e t  the parity-check mtrix of an error-locating code be the product of 
H = Hx@% = e . 0 
e e 
e e e 
. 
e e 
e e 
Then a code word of the error-locating code 
equations i n  H j  obtainable from the row vectors of k1 r2 = % - where rl = nl - satisfies all the parity-chec 
H which are of the fo  
implemented by subdivid 
check d i g i t  positions) into nl subblocks of + digi ts  each and feeding each group 
into a check digi t  calculator connected according t o  the second component code. 
The resultant check d ig i t s  of each subblock are gated by the sequence 
code word. W s  encoder i s  sham i n  Fig. 4. 
This encoding scheme maybe 
s (together with zeros i n  the 
bi1 (3;) bin(') and m d  subblock-by-subblock t o  fOMiL the check digi ts  of the 
The pzrity-check matrk o f t h e  first component code controls the gating and 
thus the sequence m a y  be generated by a shift register connected according t o  
hl(x). 
, in to  a sub-encoder (like that of Fig. 3)  as shown i n  Fig. 5. 
It can be noted that the subblock check d i g i t  calculator cswl be converted 
-5- 
. .  
I t 
Subblock Check 
d ig i t  caleulato 
component code 
f o r  second 
Switch S is at position 1 for  Wformation d ig i t s  and 2 f o r  check d ig i t s  
Fig. 4 Encoder fo r  Error-Locating Codes 
-6- 
Information Digits 
Subblock Checking 
I Digits Calculator 
1 I 
&&:h S -s at 1 fo r  i n f o m t i o n  d ig i t s  incoming and 
at 2 f o r  check digits. 
Fig, 5 Check Digit Calculation and Encoder Conversion 
Check Digits 
By changing the second component code t o  its dual there results two modes. 
Moreover, the first component code which generates the controlling sequency may 
a lso  be changed t o  its dual, 
' 
I n  t h i s  way four modes are achieved with tbe scheme 
of Fig. k .  
Eight-Mode mcoder 
An eight mode encoder i s  then achieved by carribining the encoders of Figs. 
3 a-ud 4. 
converted t o  a sub-check-digit-calculator by altering the input/crU-t;put connec - 
t ions as sham i n  Fig. 5 and the accumulating adder i s  actual lythe buffer 
storage with a single feedback loop. Hence by the addition of judiciously 
placed gates or switches we may a l t e r  the encoder t o  perform any one of eight 
encoding functions, consisting of four iterated codes and fora error-locating 
codes. 
The cambination poses - no. difFficulty because the sub-encoder may be 
For l inear codes a syndrome' calculator may be obtained by a slight m o d i f i -  
cation of the encoder, but the decoding procedure from this point on may require 
no additional c i rcui ts  or up t o  eight separate c i rcui ts  depending upon the decoding 
strategy t o  be used. 
An exanple of th i s  encoder i s  the encoder formed on the basis of a B-C-H 
(15,s) three error-correcting code (with generator matrix Gl and pa;r'-l-ty-check matrix 
H1) and the Hamming (7 ,k )  single error-correcting code (with generator matrix G2 
and pasity-check matrix H2)- 
are given i n  Table 1. 
being constructed using the ideas presented here. 
The eight r e sd tan t  codes and the i r  ‘capabilities 
An eight mode encoder/decoder has been designed and is  
’ A n  error analysis using the encoder in a b i n q  symmetric channel has also 
been performed whtch indicates how the encoder shcnitd be used w i t h  and without 
feedbkk chmnels. 
In, summation, the important advantages of t h i s  encoder are: 
(I) The encoder may be easily switched through any one’ of eight ’ 
modes, four of these being iterated codes (typically high 
redmdancy codes) and faur being the error-locating codes 
(typically low redundancy) . 
(2) The code word block length remains constant through a wide 
range of code redundancies for ease of synchmnization and 
possibly decoding. 
The encoder may be used t o  form the basis for an adaptive 
coding system, Le., low redundancy codes may be used i n  l o w  
signal-to-noise environments, and conversely. 
The encoder scheme is  optimal i n  the sense that no additional 
clock periods are rep i r ed  t o  generate a code word, e.g,, a, 
(105,16) tensor product code requires lo5 clock periods and 
no more. 
( 5 )  The encoder lends itself t o  various feedback strategies, especially 
the error-locating codes which detect the erroneous transmitted 
subblocks . 
(3) 
(4) 
-8- . 
Table 1 
Code Generator Matrix 
(15,5) .. 1 
Parity-Check Matr : MinDistar Functions 
H1 7 3-error-correcting 
4 (15 t 10 1 1-error-correcting 
2-error-detecting 
1-e r ror  -c orrec t ing 
1-error-c orrect ing 
2-error-detecting 
LO -error-c orrect ing 
i
RZ 3 
4 (7,3)* 
I -  1 %@% 21 
13-error-correcting 
14-error-detecting 
28 
5 -error-correct ing. 
6-error-detecting 
16 7-error-c orrec t fng 
8-error-detec ting 
HlO H2 i 3 I . '  
I 4 
(2at2 1- 
*Tkis code is obtained by interchanging the generating polynomial and recursive 
polynomial of the (7,k) code. 
=(s,t) denotes the code is capable of locating s erronems subblocks w i t h  no 
-(2att) denotes the code is  capable of locating 2 adjacent erroneous subblocks 
more than t errors i n  each. 
with no more than t errors i n  each. 
-9- 
Ref e renc e s 
1. P. E l i a s ,  "Error-Free Coding", IRE Transactions PGIT-4, 1954, pp. 29-37. 
2. Do Slepian, "Some Further Theory of Group Codes", B e l l  System Technicd 
J&d, 3, 1219-1252, 1960. 
3. J. K. Wolf'and E. Elspas, "Error-Locating Codes -- A New Concept i n  Error 
Coz&rol", IEEE Transactions on Information Theory, Vol. IT+, 30, 2, 
(April 1963), pp. ll3-117, 
4. S. H. Chang and L. J. Weng, "Error-bcating Codes", 1965 IEEE International 
Convention Record, Pazt 7, pp. 252-258, 
5. J. KO Wolf, "On Codes Derivable from the Tensor Product of Check Matrices", 
IEEE Transactions on Information Theory, Vol. IT-11, No. 2, (April 1965), 
pp* 281-284, 
6.  J. K. Wolf, "On an Extended Class of Error-Locating Codes", Information and 
Control, Vol. 8, No. 2, (April 1965), p p I  163-169. 
D. T. Tang, "Dual. Codes as'Variable Redundancy Codes", 1965 IEEE Inter- 
national Convention %cord, part 7, pp. 220-226. 
7. 
8. WO WO Peterson, Error-Correcting Codes, MIT Press, Cambridge, Massachrcsetts, 
1961, 
9. L. J. Weng, "On Linear Product Codes and Their Duals", Scientific Report No. 4, 
Northeastern University, Boston, Massachusetts, (August 1966). 
. .  
. .  
-10- 


Variable redundancy product coders

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