Banerjee, S

Chopra, S

Dhall, R

Krishna, C B

IACS Institutional Repository

Indian J. Phvs.81 (12), 1315-1322(2007) O fete Futuristic memory device: a theoretical modeling C B Krishna1, R Dhall2, S Chopra^ and S Banerjee3* 'Department of Electronics and Instrumentation Engineennq Birla Institute of Technology and Science, Pilani-333 031, Rajasthan India department of Electrical and Electronics Engineering, Birla Institute of Technology and Science Pilani 333 031, Rajasthan, India department of Physics Birla Institute of Technology and Science Pilani-333 031, Rajasthan, India E mail sound bits-pilani ac in Received 14 August 2007, accepted 7 September 2007 Abstract The paper presents a theoretical modelmg of a memory device that may be treated as an alternative to conventional flash memory devices based on the principle that proximity induces electric field modulation leading to a high ON-OFF current ratio, which can be used to distinguish betweent the two binary states 0 and 1 The present device is expected to operate with synthetic bilayer membrane opening up the possibility of a biocompatible memory device for the future A first order calculation of parameters, relevant fabrication steps and challenges in commercialization of this device are also presented The device has an edge over other flash and quantum-dot memories with respect to non-volatility and endurance Keywords Flash-memory, synthetic bilayer membrane, charge storage, large on-off ratio PACS NOS. 81 07.b, 81 16 -c, 73 43 Fj Conventional flash memory devices [1] base their operation on the storage of charges in a floating gate layer and the modulation of the electric field because of the stored charges leading to a threshold voltage shift that results in a distinction between the two binary states. Most devices use a poly-Si layer as the floating gate. However this enhances charge leakage and degradation of the oxide layer with repeated use. The problem occurs because the charge that is stored on the gate can leak away because of the presence of local defects in the oxide layer. To overcome this problem, it was proposed that the charge could be stored in localized quantum dots embedded in an oxide layer [2]. But it was found that even such a quantum dot memory device failed to solve the problem of Corresponding Author ©2007IACS 1316 C B Krishna, R Dhall, S Chopra and S Banerjee charge retention satisfactorily [3]. With shrinking device sizes, scaling of these devices has also become a problem due to easy tunneling with reduced tunnel barriers. The most logical step to overcome charge leakage from the storage node of a memory device is to cut out the leakage path which can be done by replacing a conventional floating gate by a suspended floating gate, similar to a MEMs structure. Application of silicon micromachining technologies to the nonvolatile memory device by using mechanical bistability of the object was proposed by Peterson [4] and later developed by Halg [5]. They are expected to be compatible to conventional Si-technology and at the same time yield high-speed operation [6]. Tsuchiya et al were first to show that Nano Electro-mechanical systems based memory devices are viable with a layer of Si-nanocrystals as suspended floating gate and they are compitable with existing Si-micro-fabrication techniques [7]. However, with organic/biological nano-systems being continuously investigated for their potential MEMs application as sensors or in nanoelectronics [8,9], the need of the day is to fabricate a device, which can dwell with Silicon and with other technologies as well Based on the idea of a suspended membrane memory device [7], in this letter, we present a realistic theoretical modeling of such a structure using MATLAB that is expected to be more versatile in its application. This would also throw light on solving the long-standing issues of flash or quantum-dot memories. The schematic of the device is shown in Figure 1. The device consists of a thin membrane capable of storing charges suspended over a conventional Si-MOSFET structure and the memory operation is subject to the two positions of the charged membrane and it is important that the membrane be adequately charged (explained later in text). The likely candidates for the purpose are a poly-silicon layer or a layer of nano-crystalline dots [2,10]. There are several reports which claim that nano-crystalline dots embedded in a matrix behave as effective charge storage centers and they can be easily charged by contact Atomic Force Microscope (AFM) [11,12]. However, there are quite a few issues, which should be addressed in the context of nano-crystalline quantum dots as charge storage centers. First, charging in quantum dots is self-limiting due to the Coulomb blockade effect [13] and they may not store adequate charge for successful operation of the device. Second, the charging of nano-crystalline dots is very sensitive to humidity and charge VOLTAGE GATE (V0) Figure 1. Schematic representation of the memory device. Futuristic memory device: a theoretical modeling 1317 leakage is enhanced in moist condition [12]. And finally, other charging methods such as application of large gate voltage as prescribed by Tsuchiya et al [7] are not user friendly The alternative would be to use synthetic bilayer membranes such as lipid bilayers as they are easily available in various charged states depending on their structure [14] It has three-fold advantages : (1) As synthetic bilayers are available in charged state, there is no need for additional charging ; (2) The total charge contained in a typical a 100 nm x 100 nm x 50 nm synthetic bilayer membrane is much above the threshold value needed for switching operation of the device [15] and, (3) The bilayers can be made to bend on application of electnc field much more easily than a layer containing nanocrystalline quantum dots to achieve bistability [16]. The fabrication process involves deposition of an oxide/nitnde layer on top of the substrate followed by the deposition of a photo-resist by spinning Etch windows are then defined on the resist. A combination of anisotropic and isotropic dry etching in proper sequence is then carried out to provide the release of the structure as suggested by Cleland and Roukes [17]. Figure 2 depicts the Scanning Electron Micrograph image of a Si02 structure in floating condition Figure 2. Air gaps are clearly observed in a SiO? structure indicated by arrows Instead of conventional memory devices, which differentiate between the two binary states based on a threshold voltage shift between the two states, here we use the ratio of the ON current (strong inversion) and the OFF current (weak inversion) to separate the two states. This is achieved by having the membrane in two stable states (bi-stability, shown in Figure 3) wherein state 1 is a rest state (stable equilibrium) whereas the second one is that of unstable equilibrium wherein an external electric field has to be applied to hold the membrane in this position. The proximity of the membrane to the substrate leads to electric field modulation in the substrate resulting in strong and weak inversion respectively that can be differentiated by the currents in the two cases. The electric field in an MOS structure is given by 4 = (Sv/Sx) = (j2kT/qLD) F(p\(f, n^jp^) 0) where 1318 C B Krishna, R Dhall, S Chopra and S Banerjee STATE 1 w „ STATE 2 weak inversion strong inversion Figure 3. The two stable states of the device (CM = charged Membrane; VG = Gate Voltage, Et = Fermi Level; Et = Intrinsic Energy Level). W: defined as zero in the bulk and measured with respect to the intrinsic Fermi level, npo*Ppo'> equilibrium carrier densities in the bulk, LD : extrinsic Debye length, k Boltzmann constant, T: Absolute temperature F(Pv,npo/Ppo) = [(e~p* +p¥-^ npo/Ppo el* - j 8 y - l ] 1 ' 2 . (2) Considering Strong inversion : y/$ = 2\j/F, Weak inversion : \j/s = 05yF , and 100% ionization (ppo = A/a, npo = nf /A/a) in the bulk. Considering the background concentration to be variable, we plot the charge on membrane required for strong and weak inversion as a function of the substrate concentration (Figure 4). The difference in the electric field leads to the high ratio between the ON/OFF current, which can be detected. One can also get an estimate about the lon/loff ratio using similar plots of ld (drain current) vs. VDS (Source-to-drain voltage) for MOSFET operation [1] in the normal and in the sub-threshold regions of operation. As weak inversion lies in the sub-threshold region Futuristic memory device: a theoretical modeling 1319 of operation an intuitive feel of the order of magnitude of difference between the two currents can be obtained. As is Ulustrated by the graphs, this has an o r f e ? Z £ t S difference of at .east (normal MOSFET current having values around mA where u b threshold currents falling in the pA region) [1]. *Ki mm-.«*» ' r~" 1 1—***-—i , , ,,, ^ * • * strong inversion »-• 1 „ 0 1 2 3 4 5 6 7 8 9 substrate concenlftfiwi (/cm3) tr~ Figure 4. Electric field required for strong and weak inversion with respect to the substrate concentration Assuming the membrane is located at a distance, d from the substrate, we can estimate the charge required on the membrane by Coulomb's models using a first order approximation. Even if the membrane is of nano-dimension, the classical Coulomb model, which is purely electrostatic in nature, remains valid for further calculations and has been used by several authors [7]. Three such values of d(10nm, 50 nm, 100 nm) are assumed and the charges required for bi-stable memory operation has been plotted as a function of the substrate concentration (Figure 5). Knowing the field required to cause weak inversion, we can again use Coulomb's model to get the value of distance d2, where d2 represents the distance between the membrane and the substrate for the second bi-stable state. For the same three values of dv the plots of the bi-stable distances vs. the substrate concentration are obtained and they are shown in Figure 6. As is evident from the plots, a high substrate concentration leads to a higher difference between the two field values but requires considerably higher charge values. Therefore the 1320 C B Krishna, R Dhall, S Chopra and S Banerjee design of the membrane involves a tradeoff between factors such as electnc field separation and charging of the membrane Moreover, as argued before, a thin suspended membrane 4 6 «ubfitrart» cons*tfr»tion {/cm3) Figure 5 Substrate concentration vs charge on membrane for different d values i , n b *» A4 ft£ 0 **• • ^ " ^ " ^-* *, < T ™ --I i D 1 mmmmtmmmmfmtmmtm i, 2 i 3 mmmmmpmmtm 1 4 i 5 i 6 • 1 7 , lOOnm I -J--j J SOnm 1 J H J lOfwn J l i t ' k 4 ii •ubltrtft « « t t M M t f » » ( & n 6 ) *«T Figure 6. Plot of bi-stable distance 'd2' as a function of substrate concentration Futuristic memory device a theoretical modeling 1321 with enhanced charge trapping capabilities would be more appropriate for the purpose However, the mechanism to get the membrane into the second bi-stable state could be through an application of an electric field The calculation of the field is a simple force balance equation between the force exerted by the electric field on the membrane and gravity This may be used as a suitable starting point for more refined calculations As estimate of the frequency of operation of the membrane has been done by calculating the resonance frequency of the beams, which are given as [17] where a) -resonance frequency, E - Young's Modulus P - density w - beam width in the direction of motion and L - beam length Taking beam dimensions being (100 nm x 100 nm x 50 nm), we arrive at a value greater than 25 GHz that is close to the value obtained for a nanometer-scale mechanical resonator [17] Though it establishes the suitability of this memory for high frequency applications there are several problems still persisting associated with the fabrication of the device and integrating it into Si-IC manufacturing processes The fabrication steps involved to arrive at the memory structure are intricate and challenging The mechanical and the elastic properties of the membrane should also be thoroughly investigated for a successful operation the device It is to be noted that the resonance frequency for a charged membrane is different from that of an uncharged one and hence suitability of a charged membrane for high frequency operations needs to be reassessed If we compare the two memory structures, conventional flash memory and the theoretically modeled memory that is expected to operate with organic/biological system, we find that in case we use the new structure as a random access memory (RAM), it is expected to provide much faster writing time as compared to flash memories where both 0 and 1 need to be written with suitable voltage application between the source and the gate Also this process provides a lesser power consumption especially if the data is biased towards one bit and we exploit this fact Problems before commercialization involve the fabrication of several membranes on a chip, pre-charging them, determining the ideal combination of substrate concentration, membrane distance and the electric field for bi-stability Investigations are already underway to address the above-mentioned issues as a suspended floating gate memory device may solve many long-standing problems of a flash memory 1322 C B Krishna, R Dhall, S Chopra and S Banerjee Acknowledgment One of the authors (CBK) acknowledges the Practice School Division, Birla Institute of Technology and Science, Pilani for their constant support. SC thanks CEERI for supporting fabrication. References [1] S M Sze Physics of Semiconductor Devices (2nd Edition) (New York • Wiley) Chapter 7 (1981) [2] S Banerjee, S Huang, T Yamanaka and S Oda J Vac Sc Technol B20 1135 (2002) [3] S Banerjee, S Huang and S Oda IEEE Transactions, Nanotech 2 88 (2005) [4] K E Pterson IBM Tech Disci Bull 20 5309 (1978) [5) B Halg IEEE Trans Electron Devices 37 2230 (1990) [6] Q Zheng and Q Jiang Phys Rev Lett 88 045503 (2002) [7] Y Tsuchiya, K Takai, N Momo, T Nagami, H Mizuta and S Oda J Appl Phys 100 094306 (2006) [8] S Kumagai, S Yoshn, K Yamada, N Matsukawa, I Fujiwara, K Iwahori and I Yamashita Appl Phys Lett 88 153103 (2006) [9] J Fragakis, S Chatzandroulis D Papadmitrtou and C Tsaonis J Physics, Conference Series 10 305 (2005) [10] L Guo, E Leobandang and S Y Chou Appl Phys Lett 70 850 (1997) [11] S Banerjee, M A Salem and S Oda Appl Phys Lett 83 3788 (2003) [12] T A Boer, L D Bell and H A Atwater Appl Phys Lett 79 791 (2001) [13] D K Ferry and S M Goodnick Transport in Nanostructures (Cambridge University Press) (1997) [14] J Fuhrhop and W Helfnch Chem Rev 93 1565 (1993) [15] V Kumaran Phys Rev Lett 85 4996 (2000) [16] T M Fischer Biophys J 63 1328 (1992) [17] A N Cleland and M L Roukes Appl Phys Lett 69 2653 (1996) 

Futuristic Memory Device : A Theoretical Modeling

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Futuristic Memory Device : A Theoretical Modeling

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