A multi-level optimization strategy to improve the performance of the stencil computation

Abstract

International audienceStencil computation represents an important numerical kernel in scientific computing. Leveraging multicore or manycore parallelism to optimize such operations represents a major challenge due both to the bandwidth demand and the low arithmetic intensity. The situation is worsened by the complexity of current architectures and the potential impact of various mechanisms (cache memory, vectorization, compilation). In this paper, we describe a multi-level optimization strategy that combines manual vectorization, space tiling and stencil composition. A major effort of this study is the comparison of our results with Pochoir stencil compiler framework. We evaluate our methodology with a set of three different compilers (Intel, Clang and GCC) on two recent generations of Intel multicore platforms. Our results show a good match with the theoretical performance models (i.e. roofline models). We also outperform Pochoir performance by a factor of x2.5 in the best cases