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Efficient Matricization of n-D Array with CUDA and Its Evaluation
Authors
G.G.M.N. Ali
M. Chafii
+3 more
P.H.J. Chong
K.M.A. Hasan
M.A.H. Shaikh
Publication date
24 August 2016
Publisher
'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Cite
Abstract
International audienceScientific and engineering computing requires operation on flooded amount of data having very high number of dimensions. Traditional multidimensional array is widely popular for implementing higher dimensional data but its' performance diminishes with the increase of the number of dimensions. On the other side, traditional row-column view is facile for implementation, imagination and visualization. This paper details a representation scheme for higher dimensional array with row-column abstraction on parallel environment. Odd dimensions contribute along row-direction and even dimensions along column direction which gives lower cost of index computation, higher data locality and parallelism. Each 2-D block of size blockIdx.x × threadIdx.x is independent of each other. Theoretically, it has no limitation with the number of dimensions and mapping algorithm is unique for any number of dimensions. Performance of the proposed matricization is measured with matrix-matrix addition, subtraction and multiplication operation. Experimental results show promising performance improvement over Traditional Multidimensional Array (TMA) and Extended Karnaugh Map Representation (EKMR). Thus the scheme can be used for implementing higher dimensional array in both general purpose and scientific computing on GPU. © 2016 IEEE
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