The imminent release of 3D XPoint memory by Intel and Micron looks set to end the long
wait for affordable persistent memory. Persistent memories combine the persistence of disk
with DRAM-like performance, blurring the traditional divide between a byte-addressable,
volatile main memory and a block-addressable, persistent storage (e.g., SSDs). One of
the most disruptive potential use cases for persistent memories is to host in-memory recoverable data structures. These recoverable data structures may be directly modified by
programmers using user-level processor load and store instructions, rather than relying on
performance sapping software intermediaries like the operating and file systems.
Ensuring the recoverability of these data structures requires programmers to have the
ability to control the order of updates to persistent memory. Current systems do not provide
efficient mechanisms (if any) to enforce the order in which store instructions update the
physical main memory. Recently proposed memory persistency models allow programmers to specify constraints on the order in which stores can be written-back to main memory.
While ordering constraints are necessary for recoverability, they are expensive to enforce
due to the high write-latencies exhibited by popular persistent memory technologies. Moreover, reasoning about recovery correctness using memory persistency models in addition
to ensuring necessary concurrency control in multi-threaded programs drastically increases
programming burden. This thesis aims at increasing the adoption of persistent memories
through a) improving the performance of recoverable data structures and b) simplifying
persistent memory programming.
Software transaction abstractions developed using recently proposed memory persistency
models are expected to be widely used by regular programmers to exploit the advantages
of persistent memory. This thesis shows that a straightforward implementation of
transactions imposes many unnecessary constraints on stores to persistent memory. This
thesis also shows how to reduce these constraints through a variety of techniques, notably,
deferring transaction commit until after locks are released, resulting in substantial performance
improvements.
Next, this thesis shows the high cost of enforcing ordering constraints using recent
x86 ISA extensions to enable persistent memory programming, an ordering model referred
to as synchronous ordering. Synchronous ordering tightly couples enforcing order with
writing back stores to main memory, but this tight coupling is often unnecessary to ensure
recoverablity. Instead, this thesis proposes delegated persist ordering, wherein ordering
requirements are communicated explicitly to the persistent memory controller via novel
enhancements to the cache hierarchy. Delegated persist ordering decouples store ordering from processor execution and cache management, significantly reducing processor stalls,
and hence, the cost of enforcing constraints.
Finally, existing memory persistency models have all been specified to be used in conjunction
with ISA-level memory models. That is, programmers must reason about recovery
correctness at the abstraction of assembly instructions, an approach which is error prone
and places an unreasonable burden on the programmer. This thesis argues for a language-level
persistency model that provides mechanisms to specify the semantics of accesses to
persistent memory as an integral part of the programming language and proposes a concrete
model, acquire-release persistency, that extends C++11s memory model to provide
persistency semantics.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136953/1/akolli_1.pd
