P systems or Membrane Computing are a type of a distributed, massively parallel and non deterministic system based on biological membranes. These systems perform a computation through transition between two consecutive configurations. As it is well known in membrane computing, a configuration consists in a m-tuple of multisets present at any moment in the existing m regions of the system at that moment time. Transitions between two configurations are performed by using evolution rules which are in each region of the system in a non-deterministic maximally parallel manner. This article shows the development of a hardware circuit of selection of active rules in a membrane of a transition P-system. This development has been researched by using the Quartus II tool of Altera Semiconductors. In the first place, the initial specifications are defined in orfer to outline the synthesis of the circuit of active rules selection. Later on the design and synthesis of the circuit will be shown, as well as, the operation tests required to present the obtained results

Gutiérrez Rodríguez, Abraham

Martínez Hernando, Víctor Jose

Mingo López, Luis Fernando de

Servicio de Coordinación de Bibliotecas de la Universidad Politécnica de Madrid

Circuit FPGA for Active Rules Selection in a Transition P 
System Región 
Víctor Martínez, Abraham Gutiérrez, and Luis Fernando de Mingo 
Abstract. P systems or Membrane Computing are a type of a distributed, mas-
sively parallel and non deterministic system based on biological membranes. 
These systems perform a computation through transition between two consecu-
tive configurations. As it is well known in membrane computing, a configura-
tion consists in a ra-tuple of multisets present at any moment in the existing m 
regions of the system at that moment time. Transitions between two configura-
tions are performed by using evolution rules which are in each región of the 
system in a non-deterministic maximally parallel manner. This article shows the 
development of a hardware circuit of selection of active rules in a membrane of 
a transition P-system. This development has been researched by using the Quar-
tus II tool of Altera Semiconductors. In the first place, the initial specifications 
are defined in orfer to outline the synthesis of the circuit of active rules selec-
tion. Later on the design and synthesis of the circuit will be shown, as well as, 
the operation tests required to present the obtained results. 
1 Theoretical Preliminaries on P-Systems 
The Membrane Computing or P Systems (created by Páun [1], [2], [3]) are computa-
tion systems based on the biomolecular processes of living cells. According to this, 
the investigations are based on the idea of the imitation of the procedures that take 
place in Nature, and their application to machines, can lead to discover and to develop 
new computation models which will give place to a new generation of intelligent 
computers. There are many papers about software tools implementing different P-
system variants [4], [5] and [6]. However, they are very interesting in order to define 
hardware implementation of these kinds of systems. Moreover, evolution of transition 
P- systems is very complícate to be translated into hardware devices due mainly to the 
membrane dissolving or membrane división capabilities of rules. 
Besides that, the non-deterministic maximally parallel manner in which rules are 
applied inside membranes is more appropriated to be implemented in digital hardware 
devices. In the case of P-systems hardware implementations only a few papers can be 
found: a Hardware Circuit for Selecting Active Rules [7], a Cluster of Computers [8], 
a Master-Slave Distributed Architecture [9] or hardware architecture based on micro-
controllers [10]. 
This article development a FPGA circuit for to select the active rules in a transition 
P-system membrane, by using the Quartus II tool of Altera Semiconductors [11]. In 
the first place, the initial specifications are defined to outline the circuit of the selec-
tion of active rules synthesis. Later on, the circuit synthesis will be shown as well as 
the functioning tests necessary to present the results we have reached. 
The definition, according to formal notation, of the membrane system used for the 
implemented prototype is shown in the following expressions: 
n=(V,ju,ah,...Ú)4, (R1,p1),...,(R4,p4),4) 
V = {a,b,c,d,e} 
M = [rfihhhUhh 
ú)¡ = aac 
Ri = {r¡: c->(c,in4), r2: c-*(b,in4), r3: a-*(a, in2)b, r4: dd- •+(a,in4)} 
Pi = { r¡>r3, r2 > r3} 
Oh = a 
R2 = {ri 
P2--= 0 
«h = cd 
R3 = {ri 
P3--= 0 
Ú)4 = Á 
R4 = {ri 
P4- = 0 
The circuit to be carried out obtains the región 1 active rules. The región 1 input 
valúes will be the objects multiset w¡, the group of rules R¡, the priority relationships 
among rules p¡ and the inner adjacent regions number (two regions in this case). The 
objects number y is 5 with decimal multiplicity (0 - 9), therefore, we will need 4 bits 
to represents each object. And so, a word representing the multiplicity of the 5 objects 
will occupy 20 bits. The rules group is formed by 4 rules which will be stored in the 
device memory. 
Each of the 4 rules we need to store in the memory will be coded with 64 bits. This 
is, 20 bits for the antecedent, 20 bits for each consequent of the two inner interior 
regions, plus 4 remaining bits used to code the priorities mask of each rule with re-
gard to the other ones. The rules are stored, therefore, in a ROM 4x64 bits memory. 
2 Hardware Implementation of Active Rules 
The logical circuit general description is obtained by means of the conjunction of 
certain fundamental elements. These elements have been denominated basic Func-
tional Units (FU's). These FU's controls the positive validation of a certain evolution 
rule in function of its applicability, utility and activation properties. The Fig. 1 show 
the general outline of the circuit based on these functional units. 
: a-*(a,in3), r2: ac-*S} 
: a -* S} 
: c-*(d,out), r2: b-*b} 
Rules 
Counter 
4x64 ROM 
Memory 
ROM word 
Sepárate 
Multiset 
Active F.U, 
Output 
Control 
5 DO 
n 8 
Applicable F.U. Useful F.U. -< 1 
Interior Región 
Exist. 
N Enables 
Rules 
Prloritles 
Active Rules 
SalldaActívo 
Fig. 1. Scheme general of the circuit to obtain the active rules of a membrane región 
Basically, the global circuit inputs are composed by the región objects multiset of 
the membrane to be evaluated, the in¡ bits to determine the interior regions existence, 
an input clock that allows going on reading and processing the memory rules and a set 
input to initialize the active rules register of the circuit. The register output shows, in 
positive logic, the active rules of the región, after processing all the ROM memory 
rules. 
In the circuit operation, the memory words will be sequentially read and the differ-
ent parts that compose each word will be sepárate. Each different part will be used in 
the corresponding ñinctional unit or sub-circuit. A counter circuit is needed to read 
sequentially the memory words. A distributor circuit will be used to sepárate the dif-
ferent groups of each word. 
The usable rule condition is checked by the Useful Functional Unit circuit. Ac-
cording to this condition, this particular circuit should check, in each rule, whether the 
consequent v of the rule has some objects which are sent to the inner adjacent regions. 
In this case, the interior región should exist. The applicability condition of an evolu-
tion rule is performed by the Applicable Functional Unit circuit. According to the 
which, the objects of its antecedent should exist in the región multiset in the same or 
bigger multiplicity. 
The Active Functional Unit is the part of the circuit in charge of evaluating the pri-
orities among all the existing rules in the membrane región. The result obtained in this 
unit is a N bits output vector (being N the number of rules). This vector contains the 
rules potentially active (bit=l) and the rules that should be inhibited in the case of 
being useful and applicable a rule of more priority that disables it (bit=0). 
3 Experimental Results 
Next we will present the results of simulating the selection of active rules circuit of 
the P system example presented in the section 1. For this example, the circuit will 
obtain the active rules of the región 1, being its two interior regions the 2 and the 4 
ones. 
On the other hand, the software Quartus II of Inc Altera includes a simulator that 
can be used to verify as much the behavior as the yield of the carried out designs. The 
Quartus II simulator allows defining input vectors that will serve as stimulus to the 
circuit inputs. The application of the input vectors in the simulation allows checking 
the state of the exits of the circuit, verifying the validity, functionality and effective-
ness of the circuit this way. 
In Quartus II, we can perform functional simulations, where the circuit output ex-
clusively depends on the inputs valúes, or we can carry out simulations of a major 
complexity and depending on time, where one or more clock signáis are defined. In 
our particular case, we are carried out the sequentially reading of the rules defined in 
ROM memory, with the help of a system clock implemented for that purpose. 
To be able to simúlate the circuit, the previously described steps for the Design and 
Synthesis ofthe Circuit of Active Rules must be fulfilled completely: 
• Creation of the project "ActiveRules" 
• Inclusión in the project of all the files with VHDL descriptions of the differ-
ent elements of the design. 
• Inclusión in the project of the schematic blocks files with the design of the 
circuit. 
• Election of the device destination: Cyclone IIEP2C35F672C6. 
• Circuit Compilation (Synthesis). 
As a previous step to the simulation execution, it is necessary to load in the ROM 
memory system the code of the defined rules for the P system región that is going to 
be simulated. In this case, the information relative to the rules group Rl7 as well as the 
priorities p¡ will be recorded in the ROM memory circuit. The consequents of the 
regions here and out, are not necessary for the functionality of the circuit, since they 
are not evaluated to determine whether a rule is applicable or not. 
The information needed to code the región rules, for a certain state, will loaded in 
words of 64 bits, according to the following distribution: 
1. The 20 bits most significant (bits 63 to 44) contain the rule antecedent. 
2. The following 20 bits (bits 43 to 24) contain the consequent for the inner re-
gión 1. 
3. The next 20 bits (bits 23 to 4) contain the consequent for the inner región 2. 
4. The last 4 bits of each word of the ROM are used to establish the mask of 
priorities among the rules defined in the membrane. 
In the circuit operation phase, once all the rules have been read sequentially and its 
evaluation (several clock pulses are needed to address the memory ROM words) has 
been completed, the Active Functional Unit circuit will be responsible for the com-
posing of all the priorities among the rules defined in the system, and for the the 
Addr 
O JCOOO OOOO D001 0000 0000 0000 0000 OCOO OCOO OCOC CDOC COOC D001 0000 0000 1101 c->(c,in2) M > r 3 
i J 0 0 0 0 oooo 0001 oooooooo oooo oooo oooo oooo DOOO DOOOOOOI oooo oooo oooo 1101 c->(b,in2) r2>r3 
2 GOOI ococ ccocoooooooo oooi oooo oooo oooo oooo oooo oooo oooo oooo oooo m i a->(b,in1) -
| oooo oooo oooo 0010 oooo oooo oooo oooo oooo oooo 0001 oooo oooo oooo oooo m i dd->[a,in2) -
Antecedent Reg. IConseq. Reg. 2 Conseq. Prionties 
Mask 
Fig. 2. Shows the method adopted to stored information into the 4x64 ROM memory of the 
rules R¡ and the priorities masks of the región 1 in the membrane example 
\building up of a final mask of priorities, which will be applied to the output vectors 
proceeding from the other two functional units. 
Finally, to check the behavior of the designed circuit, the simulation ('waveforms') 
vectors are created. They represent the type, the forms and the characteristics of the 
input signáis. In the same way, in the simulation vector the signáis representing the 
output of the circuit we want to evalúate are identified. The simulator applies the test 
vectors to the compiled design and determines the resulting valúes in the system 
outputs. 
The next step is to include the circuit inputs and outputs going to be simulated: 
• 'Sef: (input, 1 bit). Initialization input of circuit components (ROM, rules 
counter, Functional Units....) 
• 'Inl': (input, 1 bit). Existence of internal región 1. 
• 'In2': (input, 1 bit). Existence of internal región 2. 
• "w_a", "w_b", "w_c", "w_d", "w_e": (input, unsigned decimal, 4 bits). Input 
Multiset elements. 
• 'Clk': (input, 1 bit). System clock. 
• 'Activas': (output, 4 bits). Exit of the system representing the active rules. 
• 'Salida Activa' (output, 1 bit). Flag determining when the active rules output 
is stable. 
The test case shown corresponds with a computation model in which the circuit of 
active rules works together with other elements that were changing their conditions 
according to the temporary evolution of the system. So, we can introduce new alea-
tory valúes in the input vectors, by using the 'Sef flag. 
We can check how the 'SalidaActiva' is validated in irregular periods (due to the 
'Sef activations), and how it becomes stable when there are not new loads of data. 
The chronogram appeared in figure 3 shows the variation of the inputs signáis and the 
outputs result. 
The initial valúes are: 
• w_a [3..0] = 2 (decimal) --> Applicable r3 
• w_c [3..0] = 1 (decimal) --> Applicable ri and r2 
• w_d [3..0] = 3 (decimal) > Applicable r4 
• w_b, w_e = 0 
• Inl = 1 (Región 1 Exists) —> r3 is Useful 
Ops 320.0 ns 500.0 ns 
Set 1
 r in1 
in2 i 
w a \_ i \ i 
w a[3] 
w a[2] 
w_a[1 ] 
w a[0] 
w_b \_ D ! 
w b[3] 
w b[2] 
w b[1] 
w b[0] 
w_c \ ! 
w c[3] 
w c[2] 
w c[1] MI 
w_c[0] 
w_d 3 X 0 X 13 X 7 X 4 X 14 X 1 D 
w d[3] i 
w d[2] i 
w_d[1] 
w_d[0] i 
w e 0 ) 
w e[3] 
w e[2] 
w e[1] 
w e[0] 
Clk smimimiiT 
_r _r i s _r _r _r i i i J\J\J\I\J\J\IU\T I s I I I I I I s I _r _r i i i s i i i i i i I Activas 0000 i 1101 X 1100 | 0010 | 1101 ) 
Activa s[3] I I I 
Activa s[2] I i I 
Activa s[1] i I 
Activa s[0] I i I 
SalidaActiva r r ~ r r ~ 
Fig. 3. Inputs-output signáis variation 
• In2 = 1 (Región 2 Exists) —> ri, r2 and r4 are Useful 
• Clock --> Cycle lOns 
Therefore, in accordance with these conditions, the rules rh r2, r3 and r4 are all use-
ful and applicable initially. The priorities mask will be 1101, this mask disables r3. 
The initial active rules output will have the 1101 valué after 5 clock periods showing 
that the rh r2, and r4 rules are actives. 
An external initialization ('Set') changing the input vectors valúes to w_d [3..0] = 
0, would make r4 not applicable. In this case, the signal 'SalidaActiva' is annulled by a 
new change of the 'Set' signal and the load of new input valúes. It can be proved how, 
once the 50ns necessary to complete a new calculation have passed, the change takes 
place in the vector 'Activas' and one period later it becomes valid with a 1 in the 'Sali-
daActiva' signal. The obtained valúes remain stable until a new activation of 'Set' is 
produced. 
4 Conclusions and Future Remarks 
This paper presents a direct way to obtain a FPGA circuit capable to select the active 
rules inside the P-system membrane. The final step is to implement a hardware circuit 
accomplishing the outlined initial requirement. That is, given an initial multiset of 
objects, a finite set of evolution rules and an initial Active Rules, the circuit provides 
the set of rules to be applied to a membrane. The development of the digital system 
can be carried out by using hardware-software architectures as schematic blocks or 
VHDL language. The physical implementation can be accomplished on hardware 
programmable FPGA's devices. 
When analyzing the objectives reached, it can be proved that both the designs as 
much as accomplished synthesis, allow to obtain a hardware system for a general 
model of P transition system. This means that we can reach the behavior of a región 
of any membranes system with the obtained circuit. The only limitation is the máxi-
mum size of certain parameters, such as the number of rules, the multiplicity of the 
objects or the number of interior adjacent regions. 
The obtained circuit behaves based on the evolution rules stored in memory (which 
do not change during the system evolution process) and the inputs, which correspond 
with the valúes of the región state (reflected in its objects multiset). 
If the conditions of the región change, the circuit modifies its outputs being ad-
justed to the new valúes. This feature is of a supreme importance in order to intégrate 
this circuit as a module that works cooperatively together with other circuits. These 
circuits can carry out the rest of the tasks needed to complete the evolution of a transi-
tion P system. 
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Circuit FPGA for active rules selection in a transition P system region

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