InP Drain Engineering in Asymmetric InGaAs/InP MOSFETs

Abstract

The design of the InP drain layer in asymmetric InGaAs/InP MOSFETs has been studied experimentally. The influence of doping and thickness of the InP drain has been carefully measured and compared with the performance with an InGaAs drain, regarding the output conductance, the voltage gain, and the leakage current. It is shown that the introduction of an undoped InP spacer has a profound effect on the transistor characteristics. Finally, the effect of a gate-connected field plate at the InP drain side has also been studied both in dc and RF data