A new high-performance normally-off gallium nitride (GaN)-based metal-oxide-semiconductor high electron mobility transistor that employs an ultrathin subcritical 3 nm thick aluminium gallium nitride (Al0.25Ga0.75N) barrier layer and relies on an induced two-dimensional electron gas for operation is presented. Single finger devices were fabricated using 10 and 20 nm plasma-enhanced chemical vapor-deposited silicon dioxide (SiO2) as the gate dielectric. They demonstrated threshold voltages (Vth) of 3 and 2 V, and very high maximum drain currents (IDSmax) of over 450 and 650 mA/mm, at a gate voltage (VGS) of 6 V, respectively. The proposed device is seen as a building block for future power electronic devices, specifically as the driven device in the cascode configuration that employs GaN-based enhancement-mode and depletion-mode devices

Al-Khalidi, Abdullah

Brown, Raphael

Li, Xu

Macfarlane, Douglas

Ternent, Gary

Thayne, Iain

Wasige, Edward

Zhou, Haiping

English

Enlighten

n       Brown, R., Macfarlane, D., Al-Khalidi, A., Li, X., Ternent, G., Zhou, H., Thayne, I., and Wasige, E. (2014) A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT. IEEE Electron Device Letters, 35 (9). pp. 906-908. ISSN 0741-3106   Copyright © 2014 The Authors   http://eprints.gla.ac.uk/94794/       Deposited on:  09 October 2014                   Enlighten – Research publications by members of the University of Glasgow http://eprints.gla.ac.uk 906 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 9, SEPTEMBER 2014A Sub-Critical Barrier Thickness Normally-OffAlGaN/GaN MOS-HEMTRaphael Brown, Douglas Macfarlane, Abdullah Al-Khalidi, Student Member, IEEE, Xu Li,Gary Ternent, Haiping Zhou, Iain Thayne, and Edward Wasige, Member, IEEEAbstract— A new high-performance normally-off galliumnitride (GaN)-based metal–oxide–semiconductor high electronmobility transistor that employs an ultrathin subcritical3 nm thick aluminium gallium nitride (Al0.25Ga0.75N) barrierlayer and relies on an induced two-dimensional electron gasfor operation is presented. Single finger devices were fabricatedusing 10 and 20 nm plasma-enhanced chemical vapor-depositedsilicon dioxide (SiO2) as the gate dielectric. They demonstratedthreshold voltages (Vth) of 3 and 2 V, and very high maximumdrain currents (IDSmax) of over 450 and 650 mA/mm, at a gatevoltage (VGS) of 6 V, respectively. The proposed device is seen asa building block for future power electronic devices, specificallyas the driven device in the cascode configuration that employsGaN-based enhancement-mode and depletion-mode devices.Index Terms— GaN, AlGaN, MOS-HEMT, normally-off,enhancement-mode, insulated gate, PECVD SiO2.I. INTRODUCTIONGALLIUM nitride (GaN) based wide bandgap semicon-ductor transistor technologies demonstrate high break-down electric fields and high current densities, and so areactively being researched for power electronics applications.Conventional GaN-based HEMTs are of depletion mode typebut enhancement mode (E-mode) or normally-off deviceswould be preferable for power electronics since they simplifycircuit design and provide highly desirable essential feature offail-safe operation [1], [2].Common approaches to achieve normally-off GaN-basedHEMTs are based on the conventional d-mode devices(∼20nm thick AlGaN barrier (∼25% Al-content) with aninherent two dimensional electron gas (2DEG) channel) andinclude recessed-gate, fluorine ion implantation or growth ofa p-type GaN or AlGaN cap layer to locally deplete thechannel underneath the gate [2]. These approaches suffer fromnon-uniformity in device performance, device instability andManuscript received May 31, 2014; accepted June 23, 2014. Date ofpublication July 15, 2014; date of current version August 21, 2014. This workwas supported in part by the U.K. Defence Science and Technology Labo-ratory under Contract DSTLX-1000064098 and in part by the Engineeringand Physical Sciences Research Council, U.K., under Grant EP/K014471/1.The review of this letter was arranged by Editor T. Egawa.R. Brown, A. Al-Khalidi, X. Li, G. Ternent, H. Zhou, I. Thayne, andE. Wasige are with the High Frequency Electronics Group, School ofEngineering, University of Glasgow, Glasgow G12 8LT, U.K. (e-mail:edward.wasige@glasgow.ac.uk).D. Macfarlane was with the High Frequency Electronics Group, School ofEngineering, University of Glasgow, Glasgow G12 8LT, U.K. He is now withInternational Rectifier, Newport NP10 8YJ, U.K.Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2014.2334394low Vth, respectively. They generally also do not exhibit highenough Vth for power switching applications for which valuesin the range of 3–5 V are preferred in order to prevent themis-operation caused by noise.Uniform E-mode device performance can be obtainedthrough the use of a non-recessed thin barrier, i.e. an AlGaNthickness of under ∼10 nm [3]–[7]. The channel can beeasily depleted under the gate for normally-off operationdue to the reduced 2DEG density, but the devices sufferfrom reduced drain currents and high on-resistances since thelow density 2DEG is across the entire source-drain region.To reduce the access resistance between the gate-source andgate-drain regions, SiO2 passivation layers have been used inthese regions in Refs. [4] and [5]. In Ref. [6] the use of anepitaxial AlN cap layer that was selectively etched from thegate region was also demonstrated. Vth of these devices isaround 0 V.GaN MOSFETs with no gate-source and no gate-drainseparation (and without a barrier layer, i.e. no heterostructure)have been demonstrated, but suffer from high On-resistancesetc. [7]. Recently, a thin 12 nm barrier normally-offAlGaN/GaN MOS-HEMT with an overlap gate structure,i.e. also no gate-source and no gate-drain separation, andusing a thick HfO2 with a large dielectric constant as a gateinsulator was proposed [8]. The device demonstrated a Vth of+3 V and IDSmax of 730 mA/mm at VGS of 10 V. Normally-off operation was attributed to negative charge in the gatedielectric which depleted the 2DEG channel for VGS < Vth.This letter describes a high performance E-modeAlGaN/GaN MOS-HEMT similar in layout to that inRefs. [7] and [8], i.e. using the gate overlap structure, butemploying an ultrathin sub-critical 3 nm AlGaN barrierlayer and with a SiO2 gate dielectric. There is no inherent2DEG channel at the AlGaN/GaN interface in this structureas the AlGaN thickness is below that required for 2DEGformation [9]. For 25% Al-content, the critical thicknessbeyond which 2DEG forms is around 6 nm [4], [10]. Deviceswith high positive threshold voltages and high currentoperation have been demonstrated.II. DEVICE STRUCTURE AND FABRICATIONFig. 1 shows a cross-section of the proposed normally-offAlGaN/GaN metal-oxide/(insulator)-semiconductor (MOS)HEMT. It consists of a sapphire substrate, 2–5 nm AlNnucleation layer, 3 µm GaN channel, and 3 nm Al0.25Ga0.75NThis work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/BROWN et al.: SUB-CRITICAL BARRIER THICKNESS NORMALLY-OFF AlGaN/GaN MOS-HEMT 907Fig. 1. Cross-section of the proposed E-mode AlGaN/GaN device.barrier layer. The structure was grown using molecular beamepitaxy (MBE) by SVT Associates. The device consists ofsource and drain Ohmic contacts nominally overlapped by thegate contact and employs a gate dielectric. With no or lowgate-to-source voltage (VGS), there is no 2DEG channel at theAlGaN/GaN interface to allow conduction of current betweenthe drain and source contacts as the AlGaN barrier thicknessis below the critical thickness required for the formation ofsuch a channel [9]. However, if a large enough positive biasvoltage VGS is applied, it causes the formation of a quantumwell at the AlGaN/GaN interface into which electrons from thesource and drain Ohmic regions are attracted (by the positivegate voltage), effectively creating a 2DEG channel, and so thestructure is a normally-off field effect transistor. As the criticaldevice feature required for normally off operation, the AlGaNlayer, is grown epitaxially, this eliminates the drawbacksexperienced with previous techniques such as recess-etchingin which the uniformity of the etch and hence that of thethreshold voltages (Vth) is difficult to achieve. Vth is set furtherby the thickness and properties of the gate dielectric.Single finger 100 µm wide devices were fabricated totest the device concept using process modules from ourearlier work [10]. The source/drain Ohmic contacts wereformed by photolithography, metal deposition (Ti/Al/Ni/Au,30nm/180nm/40nm/100nm) and lift-off. The sample was thenannealed at 775 °C for 30 seconds and then a layer of SiO2was deposited by PECVD at 300 oC using the followingconditions: rf power of 15 watts, pressure of 1 torr, flowrate (SiH4/N2O/N2) of 7/200/85 sccm, and a deposition rateof about 70 nm/min. The gate contacts were then formedby photolithography, metal deposition (Ni/Au, 50nm/150nm)and lift-off. Ohmic bond pad patterns were then defined byphotolithography and the SiO2 dielectric etched to expose theOhmic contacts to complete the processing.III. DEVICE OUTPUT AND TRANSFER CHARACTERISTICSResults from typical devices from 2 samples are presentedhere. One sample employs a nominal 10 nm, while the other20nm thick SiO2 dielectric. Both devices employ 6 µmlong and 100 µm wide gates. Output and transfer devicecharacteristics as well as the transconductance were measuredusing Agilent’s Device Analyzer B1500A. Fig. 2(a) shows theoutput characteristics of the device with 10 nm thick SiO2 gatedielectric which demonstrated IDSmax of over 450 mA/mmat Vgs = 6 V and Vds = 10 V. Fig. 2(b) shows the outputFig. 2. (a) Output characteristics of an E-mode 6µm × 100µm AlGaN/GaNMOS-HEMT with 10 nm thick SiO2 gate dielectric. Note the (near) zerodrain currents for VGS of 0V, 1V, 2V, and 3V. (b) Output characteristicsof an E-mode 6µm × 100µm AlGaN/GaN MOS-HEMT with 20 nm thickSiO2 gate dielectric. Drain current traces for VGS of 0V, 1V, and 2V areoverlapping.characteristics of the device with 20 nm thick dielectric.This device demonstrated IDSmax of over 650 mA/mm atVgs = 6V and Vds = 8V. The measured currents arecomparable to those of conventional depletion-mode devicesdemonstrating the equally good properties of an induced2DEG channel (these are being quantified in on-going work).A procedure to extract contact resistances for thisnon-conducting structure (when no 2DEG is present) isbeing developed, but the low knee voltages indicate goodcontacts.Transfer characteristics and transconductance at low drainbias voltages for the devices whose output characteristicsare shown in Fig. 2(a) and (b) are plotted in Fig. 3. Thethreshold voltages are +3V and +2V (estimated at 1µA/mm)for the 10 nm and 20 nm thick gate dielectric devices. Theenhancement-mode nature of the devices can be seen fromthese characteristics. The drop in threshold voltage with higherthickness of the SiO2 may be due to the SiO2 having positivecharge, increased film stress etc.IV. OFF-STATE BREAKDOWN CHARACTERISTICSOff-state (VGS = 0 V) breakdown characteristics are shownin Fig. 4. The breakdown voltages were 9 V and 17 Vfor the devices with 10 nm and 20 nm thick SiO2 gate908 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 9, SEPTEMBER 2014Fig. 3. Transfer characteristics and transconductance of E-mode AlGaN/GaNMOS-HEMTs at low drain bias voltages of 1 V and 3 V.Fig. 4. Breakdown characteristics of E-mode 6µm × 100µm AlGaN/GaNMOS-HEMTs with 10 nm and 20 nm thick SiO2 gate dielectrics.Fig. 5. Variation of the threshold voltage of the proposed E-modeMOS-HEMT employing 20 nm thick SiO2 gate dielectric with stress time.dielectrics, respectively. The current rises sharply from about1mA/mm to over 1000 mA/mm (set by equipment compliance)on breakdown. The measured breakdown field of ∼9 MV/cmsuggests that device breakdown is limited by the dielectricthickness, as seen in devices of similar geometry [7].V. DEVICE RELIABILITYDevices with 20 nm SiO2 gate dielectric were assessed forstability. A stress test with IDS = 30 mA/mm and VDS = 10 Vwas performed at 10 minute intervals. Fig. 5 shows thevariation of the threshold voltage, Vth with stress time.Vth increased by 0.25V within the first hour and continued torise with stress time, and increased by ∼1.25V after 10 hours.Device stability is being investigated via capacitance-voltagetechniques for atomic layer deposited (ALD) high-k dielectricsnamely alumina, hafnia and zirconia that are deemed the bestsuited for this device structure. Note that similar instability isa present problem in other insulated gate GaN devices [11].VI. CONCLUSIONWe have fabricated high performance enhancement-modeAlGaN/GaN HEMTs on a sapphire substrate. The proposeddevice relies on an induced 2DEG for operation. The fabri-cation is repeatable and reproducible. The proposed devicecould be used to replace the low-voltage enhancement-modesilicon transistor used to drive the high-voltage depletion-modetransistor in the hybrid high-voltage cascoded GaN switchconfiguration [12]. On-going work is focused on improvingthe stability of the devices and on realising and characterisinglarger gate periphery and high breakdown voltage all-GaNcascode devices on silicon substrates.ACKNOWLEDGMENTThe authors thank staff of the James Watt NanofabricationCentre (JWNC) at the University of Glasgow for help infabricating the devices reported in this letter. They also thankDr. M. Caesar, Prof. M. Uren, and Prof. M. Kuball of theCentre for Device Thermography and Reliability (CDTR) atBristol University for evaluating the stability of the devices.REFERENCES[1] M. J. Scott, J. Li, and J. Wang, “Applications of gallium nitride in powerelectronics,” in Proc. IEEE Power Energy Conf. Illinois, Feb. 2013,pp. 1–7.[2] J. Millán et al., “A survey of wide band gap semiconductor devices,”IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2155–2163, May 2014.[3] T. Hashizume et al., “Al2O3 Insulated-gate structure for AlGaN/GaNheterostructure field effect transistors having thin AlGaN barrier layers,”Jpn. J. Appl. Phys., vol. 43, no. 6B, pp. L777–L779, 2004.[4] A. Endoh et al., “Non-recessed-gate enhancement-mode AlGaN/GaNhigh electron mobility transistors with high RF performance,” Jpn. J.Appl. Phys., vol. 43, no. 4B, pp. 2255–2258, 2004.[5] Y. Ohmaki et al., “Enhancement-mode AlGaN/AlN/GaN high electronmobility transistor with low on-resistance and high breakdown voltage,”Jpn. J. Appl. Phys., vol. 45, nos. 42–45, pp. L1168–L1170, 2006.[6] T. J. Anderson et al., “An AlN/ultrathin AlGaN/GaN HEMT structurefor enhancement-mode operation using selective etching,” IEEE ElectronDevice Lett., vol. 30, no. 12, pp. 1251–1253, Dec. 2009.[7] K. Matocha, T. P. Chow, and R. J. Gutmann, “High-voltage normally offGaN MOSFETs on sapphire substrates,” IEEE Trans. Electron Devices,vol. 52, no. 1, pp. 6–10, Jan. 2005.[8] S. Sugiura et al., “Normally-off AlGaN/GaN MOSHFETs with HfO2gate oxide,” Phys. Status Solidi (C), vol. 5, no. 6, pp. 1923–1925,May 2008.[9] O. Ambacher et al., “Two-dimensional electron gases inducedby spontaneous and piezoelectric polarization charges in N- andGa-face AlGaN/GaN heterostructures,” J. Appl. Phys., vol. 85, no. 6,pp. 3222–3233, Mar. 1999.[10] S. Taking, “AlN/GaN MOS-HEMTs technology,” Ph.D. dissertation,Dept. Sci. Eng., Univ. Glasgow, Glasgow, U.K., 2012.[11] Y. Lu et al., “Characterization of VT -instability in enhancement-modeAl2O3-AlGaN/GaN MISHEMTs,” Phys. Status Solidi (C), vol. 10,no. 11, pp. 1397–1400, Nov. 2013.[12] J. J. Zhang, “GaN-based device cascoded with an integratedFET/Schottky diode device,” U.S. Patent 8 084 783, Dec. 27, 2011.

A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT

Enlighten: Publications

n 
 
 
 
 
 
 
Brown, R., Macfarlane, D., Al-Khalidi, A., Li, X., Ternent, G., Zhou, 
H., Thayne, I., and Wasige, E. (2014) A sub-critical barrier thickness 
normally-off AlGaN/GaN MOS-HEMT. IEEE Electron Device Letters, 35 
(9). pp. 906-908. ISSN 0741-3106 
 
 
Copyright © 2014 The Authors 
 
 
http://eprints.gla.ac.uk/94794/  
 
 
 
 
 
Deposited on:  09 October 2014 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Enlighten – Research publications by members of the University of Glasgow 
http://eprints.gla.ac.uk 
906 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 9, SEPTEMBER 2014
A Sub-Critical Barrier Thickness Normally-Off
AlGaN/GaN MOS-HEMT
Raphael Brown, Douglas Macfarlane, Abdullah Al-Khalidi, Student Member, IEEE, Xu Li,
Gary Ternent, Haiping Zhou, Iain Thayne, and Edward Wasige, Member, IEEE
Abstract— A new high-performance normally-off gallium
nitride (GaN)-based metal–oxide–semiconductor high electron
mobility transistor that employs an ultrathin subcritical
3 nm thick aluminium gallium nitride (Al0.25Ga0.75N) barrier
layer and relies on an induced two-dimensional electron gas
for operation is presented. Single finger devices were fabricated
using 10 and 20 nm plasma-enhanced chemical vapor-deposited
silicon dioxide (SiO2) as the gate dielectric. They demonstrated
threshold voltages (Vth) of 3 and 2 V, and very high maximum
drain currents (IDSmax) of over 450 and 650 mA/mm, at a gate
voltage (VGS) of 6 V, respectively. The proposed device is seen as
a building block for future power electronic devices, specifically
as the driven device in the cascode configuration that employs
GaN-based enhancement-mode and depletion-mode devices.
Index Terms— GaN, AlGaN, MOS-HEMT, normally-off,
enhancement-mode, insulated gate, PECVD SiO2.
I. INTRODUCTION
GALLIUM nitride (GaN) based wide bandgap semicon-ductor transistor technologies demonstrate high break-
down electric fields and high current densities, and so are
actively being researched for power electronics applications.
Conventional GaN-based HEMTs are of depletion mode type
but enhancement mode (E-mode) or normally-off devices
would be preferable for power electronics since they simplify
circuit design and provide highly desirable essential feature of
fail-safe operation [1], [2].
Common approaches to achieve normally-off GaN-based
HEMTs are based on the conventional d-mode devices
(∼20nm thick AlGaN barrier (∼25% Al-content) with an
inherent two dimensional electron gas (2DEG) channel) and
include recessed-gate, fluorine ion implantation or growth of
a p-type GaN or AlGaN cap layer to locally deplete the
channel underneath the gate [2]. These approaches suffer from
non-uniformity in device performance, device instability and
Manuscript received May 31, 2014; accepted June 23, 2014. Date of
publication July 15, 2014; date of current version August 21, 2014. This work
was supported in part by the U.K. Defence Science and Technology Labo-
ratory under Contract DSTLX-1000064098 and in part by the Engineering
and Physical Sciences Research Council, U.K., under Grant EP/K014471/1.
The review of this letter was arranged by Editor T. Egawa.
R. Brown, A. Al-Khalidi, X. Li, G. Ternent, H. Zhou, I. Thayne, and
E. Wasige are with the High Frequency Electronics Group, School of
Engineering, University of Glasgow, Glasgow G12 8LT, U.K. (e-mail:
edward.wasige@glasgow.ac.uk).
D. Macfarlane was with the High Frequency Electronics Group, School of
Engineering, University of Glasgow, Glasgow G12 8LT, U.K. He is now with
International Rectifier, Newport NP10 8YJ, U.K.
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2014.2334394
low Vth, respectively. They generally also do not exhibit high
enough Vth for power switching applications for which values
in the range of 3–5 V are preferred in order to prevent the
mis-operation caused by noise.
Uniform E-mode device performance can be obtained
through the use of a non-recessed thin barrier, i.e. an AlGaN
thickness of under ∼10 nm [3]–[7]. The channel can be
easily depleted under the gate for normally-off operation
due to the reduced 2DEG density, but the devices suffer
from reduced drain currents and high on-resistances since the
low density 2DEG is across the entire source-drain region.
To reduce the access resistance between the gate-source and
gate-drain regions, SiO2 passivation layers have been used in
these regions in Refs. [4] and [5]. In Ref. [6] the use of an
epitaxial AlN cap layer that was selectively etched from the
gate region was also demonstrated. Vth of these devices is
around 0 V.
GaN MOSFETs with no gate-source and no gate-drain
separation (and without a barrier layer, i.e. no heterostructure)
have been demonstrated, but suffer from high On-resistances
etc. [7]. Recently, a thin 12 nm barrier normally-off
AlGaN/GaN MOS-HEMT with an overlap gate structure,
i.e. also no gate-source and no gate-drain separation, and
using a thick HfO2 with a large dielectric constant as a gate
insulator was proposed [8]. The device demonstrated a Vth of
+3 V and IDSmax of 730 mA/mm at VGS of 10 V. Normally-
off operation was attributed to negative charge in the gate
dielectric which depleted the 2DEG channel for VGS < Vth.
This letter describes a high performance E-mode
AlGaN/GaN MOS-HEMT similar in layout to that in
Refs. [7] and [8], i.e. using the gate overlap structure, but
employing an ultrathin sub-critical 3 nm AlGaN barrier
layer and with a SiO2 gate dielectric. There is no inherent
2DEG channel at the AlGaN/GaN interface in this structure
as the AlGaN thickness is below that required for 2DEG
formation [9]. For 25% Al-content, the critical thickness
beyond which 2DEG forms is around 6 nm [4], [10]. Devices
with high positive threshold voltages and high current
operation have been demonstrated.
II. DEVICE STRUCTURE AND FABRICATION
Fig. 1 shows a cross-section of the proposed normally-off
AlGaN/GaN metal-oxide/(insulator)-semiconductor (MOS)
HEMT. It consists of a sapphire substrate, 2–5 nm AlN
nucleation layer, 3 µm GaN channel, and 3 nm Al0.25Ga0.75N
This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/
BROWN et al.: SUB-CRITICAL BARRIER THICKNESS NORMALLY-OFF AlGaN/GaN MOS-HEMT 907
Fig. 1. Cross-section of the proposed E-mode AlGaN/GaN device.
barrier layer. The structure was grown using molecular beam
epitaxy (MBE) by SVT Associates. The device consists of
source and drain Ohmic contacts nominally overlapped by the
gate contact and employs a gate dielectric. With no or low
gate-to-source voltage (VGS), there is no 2DEG channel at the
AlGaN/GaN interface to allow conduction of current between
the drain and source contacts as the AlGaN barrier thickness
is below the critical thickness required for the formation of
such a channel [9]. However, if a large enough positive bias
voltage VGS is applied, it causes the formation of a quantum
well at the AlGaN/GaN interface into which electrons from the
source and drain Ohmic regions are attracted (by the positive
gate voltage), effectively creating a 2DEG channel, and so the
structure is a normally-off field effect transistor. As the critical
device feature required for normally off operation, the AlGaN
layer, is grown epitaxially, this eliminates the drawbacks
experienced with previous techniques such as recess-etching
in which the uniformity of the etch and hence that of the
threshold voltages (Vth) is difficult to achieve. Vth is set further
by the thickness and properties of the gate dielectric.
Single finger 100 µm wide devices were fabricated to
test the device concept using process modules from our
earlier work [10]. The source/drain Ohmic contacts were
formed by photolithography, metal deposition (Ti/Al/Ni/Au,
30nm/180nm/40nm/100nm) and lift-off. The sample was then
annealed at 775 °C for 30 seconds and then a layer of SiO2
was deposited by PECVD at 300 oC using the following
conditions: rf power of 15 watts, pressure of 1 torr, flow
rate (SiH4/N2O/N2) of 7/200/85 sccm, and a deposition rate
of about 70 nm/min. The gate contacts were then formed
by photolithography, metal deposition (Ni/Au, 50nm/150nm)
and lift-off. Ohmic bond pad patterns were then defined by
photolithography and the SiO2 dielectric etched to expose the
Ohmic contacts to complete the processing.
III. DEVICE OUTPUT AND TRANSFER CHARACTERISTICS
Results from typical devices from 2 samples are presented
here. One sample employs a nominal 10 nm, while the other
20nm thick SiO2 dielectric. Both devices employ 6 µm
long and 100 µm wide gates. Output and transfer device
characteristics as well as the transconductance were measured
using Agilent’s Device Analyzer B1500A. Fig. 2(a) shows the
output characteristics of the device with 10 nm thick SiO2 gate
dielectric which demonstrated IDSmax of over 450 mA/mm
at Vgs = 6 V and Vds = 10 V. Fig. 2(b) shows the output
Fig. 2. (a) Output characteristics of an E-mode 6µm × 100µm AlGaN/GaN
MOS-HEMT with 10 nm thick SiO2 gate dielectric. Note the (near) zero
drain currents for VGS of 0V, 1V, 2V, and 3V. (b) Output characteristics
of an E-mode 6µm × 100µm AlGaN/GaN MOS-HEMT with 20 nm thick
SiO2 gate dielectric. Drain current traces for VGS of 0V, 1V, and 2V are
overlapping.
characteristics of the device with 20 nm thick dielectric.
This device demonstrated IDSmax of over 650 mA/mm at
Vgs = 6V and Vds = 8V. The measured currents are
comparable to those of conventional depletion-mode devices
demonstrating the equally good properties of an induced
2DEG channel (these are being quantified in on-going work).
A procedure to extract contact resistances for this
non-conducting structure (when no 2DEG is present) is
being developed, but the low knee voltages indicate good
contacts.
Transfer characteristics and transconductance at low drain
bias voltages for the devices whose output characteristics
are shown in Fig. 2(a) and (b) are plotted in Fig. 3. The
threshold voltages are +3V and +2V (estimated at 1µA/mm)
for the 10 nm and 20 nm thick gate dielectric devices. The
enhancement-mode nature of the devices can be seen from
these characteristics. The drop in threshold voltage with higher
thickness of the SiO2 may be due to the SiO2 having positive
charge, increased film stress etc.
IV. OFF-STATE BREAKDOWN CHARACTERISTICS
Off-state (VGS = 0 V) breakdown characteristics are shown
in Fig. 4. The breakdown voltages were 9 V and 17 V
for the devices with 10 nm and 20 nm thick SiO2 gate
908 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 9, SEPTEMBER 2014
Fig. 3. Transfer characteristics and transconductance of E-mode AlGaN/GaN
MOS-HEMTs at low drain bias voltages of 1 V and 3 V.
Fig. 4. Breakdown characteristics of E-mode 6µm × 100µm AlGaN/GaN
MOS-HEMTs with 10 nm and 20 nm thick SiO2 gate dielectrics.
Fig. 5. Variation of the threshold voltage of the proposed E-mode
MOS-HEMT employing 20 nm thick SiO2 gate dielectric with stress time.
dielectrics, respectively. The current rises sharply from about
1mA/mm to over 1000 mA/mm (set by equipment compliance)
on breakdown. The measured breakdown field of ∼9 MV/cm
suggests that device breakdown is limited by the dielectric
thickness, as seen in devices of similar geometry [7].
V. DEVICE RELIABILITY
Devices with 20 nm SiO2 gate dielectric were assessed for
stability. A stress test with IDS = 30 mA/mm and VDS = 10 V
was performed at 10 minute intervals. Fig. 5 shows the
variation of the threshold voltage, Vth with stress time.
Vth increased by 0.25V within the first hour and continued to
rise with stress time, and increased by ∼1.25V after 10 hours.
Device stability is being investigated via capacitance-voltage
techniques for atomic layer deposited (ALD) high-k dielectrics
namely alumina, hafnia and zirconia that are deemed the best
suited for this device structure. Note that similar instability is
a present problem in other insulated gate GaN devices [11].
VI. CONCLUSION
We have fabricated high performance enhancement-mode
AlGaN/GaN HEMTs on a sapphire substrate. The proposed
device relies on an induced 2DEG for operation. The fabri-
cation is repeatable and reproducible. The proposed device
could be used to replace the low-voltage enhancement-mode
silicon transistor used to drive the high-voltage depletion-mode
transistor in the hybrid high-voltage cascoded GaN switch
configuration [12]. On-going work is focused on improving
the stability of the devices and on realising and characterising
larger gate periphery and high breakdown voltage all-GaN
cascode devices on silicon substrates.
ACKNOWLEDGMENT
The authors thank staff of the James Watt Nanofabrication
Centre (JWNC) at the University of Glasgow for help in
fabricating the devices reported in this letter. They also thank
Dr. M. Caesar, Prof. M. Uren, and Prof. M. Kuball of the
Centre for Device Thermography and Reliability (CDTR) at
Bristol University for evaluating the stability of the devices.
REFERENCES
[1] M. J. Scott, J. Li, and J. Wang, “Applications of gallium nitride in power
electronics,” in Proc. IEEE Power Energy Conf. Illinois, Feb. 2013,
pp. 1–7.
[2] J. Millán et al., “A survey of wide band gap semiconductor devices,”
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A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT

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