https://www.scopus.com/inward/record.url?eid=2-s2.0-84945151182&partnerID=40&md5=6ddf5c2778c6b512bf6531ff81a9fd36A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130nm low-power CMOS process, with an operation frequency of 100MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required

Cerdas-Robles, Roberto

Chacón-Rodríguez, Alfonso

Julián, Pedro

Rodríguez, Agustín

Roberto Cerdas-Robles

Agustin Rodriguez

Alfonso Chacon-Rodriguez

Pedro Julian

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Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

Repositorio Institucional del Instituto Tecnologico de Costa Rica

Design of an IDM-Based Determinant computingunit for a 130nm low power CMOS ASIC acousticlocalization processorRoberto Cerdas-Robles∗, Agustı´n Rodrı´guez†, Alfonso Chacon-Rodrı´guez∗, and Pedro Julia´n †∗Escuela de Ingenierı´a Electro´nica, Tecnolo´gico de Costa RicaEmail: {rcerdas, alchacon}@itcr.ac.cr†Instituto de Investigaciones en Ingenierı´a Ele´ctrica, IIIE (UNS-CONICET)Departamento de Ingenierı´a Ele´ctrica y de ComputadorasUniversidad Nacional del Sur, Bahı´a Blanca, ArgentinaEmail: rodrijuana@gmail.com, pjulian@uns.edu.arAbstract—A determinant computing circuit in ﬂoating pointformat has been designed and tested for use in a CMOS ASICacoustic localization processor. The Internal Division Method(IDM) was used to implement the operation, employing amodiﬁed SRT radix-4 circuit for division operations. The unit wasdesigned for VLSI implementation in a commercial 130nm low-power CMOS process, with an operation frequency of 100MHz.The algorithm employed is parallelizable for future prototypes,should a higher operation frequency be required.Index Terms—Acoustic Localization, Multichannel Cross Cor-relation Coefﬁcient, TDOA, Low Power VLSI, FPGA, UVM.I. INTRODUCTIONThe use of an acoustic localization system has been pro-posed as part of a design of a redundant sensor network forlocalization of moving vehicles [1]. It has been demonstratedthat the phase difference between separately captured signalsin an array formed by two or more microphones can beused to estimate the angle of a sound source with respectto the array [2], [3]. Three algorithms for Time Differenceof Arrival (TDOA) estimation were evaluated and comparedin a previous work [4]. The algorithm chosen to solve theproblem stated requires the computation of determinants aspart of the estimation process. This document presents aproposal for the implementation of this determinant computingunit in a commercial 130nm low-power CMOS process, toevaluate the suitability of the chosen arithmetic architecturesin regards to area, power, and maximum operation frequencyas part of an acoustic localization processor. Section II of thisdocument brieﬂy explains the fundamentals of the algorithmthe determinant unit will be used in, to provide the reader witha frame of reference for the selected constraints. Section IIIdetails the elaboration of the ﬂoating-point division unit, andthe custom architecture used for implementation of the SRTalgorithm. Section IV describes the determinant computationunit’s design. Section V summarizes the results obtainedwhen the design was veriﬁed using a UVM approach ona XC7A100T FPGA Device, as well as Synopsys DesignCompiler’s synthesis results on the chosen technology. Finally,Section VI brieﬂy adds concluding remarks and observations,as well as recommendations for further improvements of theunit under study.II. DESCRIPTION OF THE MCCC ALGORITHMThe Multichannel Cross Correlation Coefﬁcient is an al-gorithm that allows estimation of delay-of-arrival or time-difference-of-arrival (DOA or TDOA, respectively) of a sourcesignal to a microphone array. Unlike either regular or gener-alized cross correlation methods, MCCC considers data frommore than two channels at a time, resulting in a more robustapproximation of DOA [5]. Assume a microphone array whosemicrophones are equidistant from each other, and the soundsource is located in the far plane; τn1 = Fn(τ) is the delaybetween the ﬁrst and nth microphones at a given source angleand, for an equidistant linear array, delay to each microphoneis given by:Fn(τ) = (n− 1)τ12 (1)For an array with N microphones, the input signal vectoris:ya(k, p) = [y1(k)y2(k + F2(p) · · · yN (k + FN (p)] (2)with p a hypothetical TDOA. The cross correlation functionbetween any two signals in the array is:rCCyiyj(p) = E[yi(k)yj(k + Fj(p)] (3)The spatial correlation matrix for a microphone array isdeﬁned as:Ra(p) =⎡⎢⎢⎢⎣σ21 ry1y2(p) · · · ry1yn(p)ry2y1(p) σ22 · · · ry2yn(p)....... . ....ryny1(p) ryny2(p) · · · σ2n⎤⎥⎥⎥⎦ (4)It can be demonstrated, as in [5], that the hypotheticalTDOA p that satisﬁes p = τ12 is the same p that satisﬁesargmin{Ra(p)}. Once the TDOA is found, the angle ofarrival θ may be found as978-1-4799-8332-2/15/$31.00 ©2015 IEEEθ = cos−1(dcτ12) (5)with c the speed of sound in m/s, and d the distance betweenmicrophones in the array [6].III. DESCRIPTION OF DIVISION COMPUTING UNITFloating point computing of divisions is required as part ofthe determinant estimation process, as the reciprocal functionf(x)−1 is needed. The SRT algorithm is employed. The max-imum redundancy Radix-4 variant was chosen and modiﬁedto calculate eight quotient bits per clock cycle, by replicatingthe quotient computation adders four times. The equation thatdescribes the result of each adder is:Ri+1 = 4Ri + qi ∗D (6)in which qi is the quotient bit generated by each adder stage.When maximum redundancy is used, seven possible quotientscan be generated, qi ∈ [−3,−2,−1, 0, 1, 2, 3]. The termquotient bit refers to a bit in redundant notation, as opposed tobinary notation. Each quotient bit requires three actual bits torepresent its value in binary [7]. The block accepts any inputvalue x in the range x ∈]0, 2[The block, coded in Verilog, was designed to accept 16input bits, in ﬁxed-point notation, with 15 fractional bits. Theoutput range is therefore in the range y ∈]0.5; 215[This input range was chosen to use the block with ahalf-precision ﬂoating point number’s mantissa. Due to therestrictions of the SRT algorithm, which state that the partialresult may never exceed four times the value of the divisor,the operation is physically implemented as y = 0.5x ∗ 2. Thismultiplication can easily be implemented by performing ashift operation after the division has been computed. Figure 1presents the block diagram of the designed divisor’s datapath.IV. DESCRIPTION OF THE DETERMINANT COMPUTINGUNITThe system was implemented with the capacity to evalu-ate fourth-order matrixes, which correspond to spatial crosscorrelation matrixes generated by arrays of four microphones.A. Algorithm usedThe algorithm employed is the internal division method(IDM) described in [8], and described in Verilog. It is aparallelizable methodology that can be used to estimate thedeterminant of any square matrix of order n, as long asthe matrix’s ﬁrst element is not zero. The algorithm is ageneralization of Chio’s rule. The determinant is estimated bybreaking up the matrix into second order sub-determinants,which are then used to ﬁnd the determinant. The algorithmwas implemented sequentially to reduce area use and minimizepower consumption. The algorithm can be summarized asfollows:1) Isolate the ﬁrst row and ﬁrst column of the matrix.Figure 1. Block diagram of the designed division unit’s datapath, using aradix-4 SRT structure replicated four times to estimate eight quotient bits perclock cycle.2) Form (n − 1)2 second order submatrixes, combiningeach element of the matrix with the ﬁrst element of thematrix, the ﬁrst element of its row, and the ﬁrst elementof its column. Ignore the elements present in either theﬁrst row or the ﬁrst column.3) Calculate the determinant of each second order subma-trix.4) Divide each calculated subdeterminant by the matrix’sﬁrst element to normalize them.5) Replace each element that produced a submatrix by theresult obtained from the last step.6) Repeat the process, ignoring one additional row and oneadditional column, until n = 2.7) Multiply all elements belonging to the diagonal of theresulting matrix. This value is the determinant of thematrix.B. Data representationDue to the precision required by determinant computationsto accurately predict the angle of arrival, ﬂoating point rep-resentation of data is required to minimize the system’s wordwidth. A modiﬁed IEEE 754 half-precision ﬂoating point(16 bit) format was employed, using an explicit hidden bit(which is implicitly set to one in the standard implementa-tion) to facilitate the FPU unit’s design. Five bits were usedfor exponent representation; as in the standard format, theexponent is represented with an offset to avoid the need fortwo’s complement representation. Ten bits were employed torepresent the mantissa. The last bit is reserved for to representthe number’s sign. Using this format allows for representationof numbers between −215 and 215, with a maximum resolutionof 2−9 bits in the mantissa.C. Datapath’s architectureFigure 2 presents a simpliﬁed block diagram of the deter-minant computing unit’s datapath. A normalizer is inserted inthe FPU unit along with the SRT algorithm detailed in theprevious section, to automatically truncate results to the tenmost signiﬁcant bits. A simple circuit implementing the SPIprotocol is used to interface both the input and output shownwith any outside master unit.Figure 2. Simpliﬁed block diagram of determinant computing unit datapath.Each register bank has two reading address inputs to access data on two sep-arate channels. The reading address pattern is generated using two counters.V. RESULTSThe design was validated using an UVM veriﬁcation envi-ronment written in System Verilog [9]. Random data sequenceswere generated and driven into the determinant calculator, andresponses were compared via a scoreboard to the reference’sresults. Determinants were found to be within 5% of theexpected value for a 10-bit mantissa. Figure 3 shows theveriﬁcation environment used. To speed up the validation, thedesign was synthesized on a XC7A100T FPGA. Test vectorswere applied to the DUT on the FPGA via an SPI interface.Table I shows synthesis results on the FPGA.Table II presents the post-synthesis results obtained usingSynopsys Design Compiler, after porting the Verilog codeto a low power standard cell library for a 130nm CMOScommercial process. In both cases, the critical delay path isthe data route through the normalizer unit in the FPU afterencountering a division. Power consumption is signiﬁcantlyreduced when using the low-power standard cells library.To evaluate the circuit’s performance within the context ofthe desired application, a linear array of four microphoneswas prepared and deployed in a woodworking workshop.A wood-polishing machine positioned 5m away from theFigure 3. UVM environment used for veriﬁcation of the determinant com-puting unit [9].Table ISUMMARY OF SYNTHESIS RESULTS FOR XC7A100T FPGA.TimingCritical delay time (nS) 12, 231Maximum operation frequency (MHz) 81, 759PowerTotal power (mW) 65, 13Dynamic power (mW) 22, 69Static power (mW) 42, 44AreaRegisters 483LUTs 1742I/O Blocks 7Percentage of available resources used 4%Table IISUMMARY OF POST-SYNTHESIS RESULTS AFTER PORTING THE CODE TO ALOW POWER STANDARD CELL LIBRARY FOR A 130NM CMOSCOMMERCIAL PROCESS. DATA REPORTED BY SYNOPSYS DESIGNCOMPILER.TimingCritical delay time (nS) 9.67Maximum operation frequency (MHz) 103.41PowerTotal power (mW) 0.8439Dynamic power (mW) 0.8438Static power (mW) 81.53x10−6Area(Values given in terms of a NOR gate area)Combinational 57372.48Sequential 18106.56I/O Pads 7Total area 70128.00array was used as the source signal, sampled at 32 kHzfor 30 second intervals. The four microphones were spacedlinearly, with a spacing of 1m between each device in thearray. The angle of arrival of the signal to the array wasvaried by rotating the array along its horizontal axis seventimes. 200 hypothetical delay values were evaluated in eachcase, to account for sources located between 0◦ and 180◦.Results were calculated using the MCCC method described inprevious sections; theoretical data was derived using MATLABto calculate the determinant of the cross-correlation matrix,and compared to the results of utilizing the proposed circuitto estimate the determinant instead. Table III summarizes theresults obtained for each of the seven measurements. The samedata is presented graphically in ﬁgure 4.Table IIIANGLE OF ARRIVAL ESTIMATION FOR THEORETICAL AND EXPERIMENTALCASES.Theoretical angle Experimental angle29.31◦ 47.11◦41.9◦ 168◦46.27◦ 60◦64.83◦ 78.34◦78.34◦ 66.83◦82◦ 85.73◦88.78◦ 90◦Discrepancies between theoretical and experimental datacould arise as a result of lower precision in the circuit’sarithmetic operations; the determinant calculator’s responseaccuracy is bound by the amount of bits in the represen-tation’s mantissa, while MATLAB has no such constraint.More signiﬁcantly, however, is the variation in TDOA betweenthe peak angle value and the minimum value: approximately500μs. At lower sample rates, an error of one sample becomesmore signiﬁcant, with each sample representing a greatertime displacement. Complicating this issue, the relationshipbetween the angle of arrival and TDOA is non-linear; forangles below 60◦, decreasing the angle results in a fast non-linear decline in the expected TDOA as a result of the cosineterm present in Eq. (5). This explains the increasing accuracyas the angle approached 90◦. Therefore, as proven in [6], thesampling frequency must be increased to at least 200 kHzin order to get accurate results to within one degree for theentire angle range. One can thus safely assume that the errorin these tests was merely the low data sampling used, andnot a problem within the determinant computing units. Testsusing a 200kHz sampling speed were being performed as ofthe writing of this paper, to settle the issue.VI. CONCLUSIONSThis document presents the implementation of a functionalprototype of a determinant computing unit for fourth-ordermatrixes, which allows for evaluation of the selected arithmeticarchitectures in the desired application. Modifying the zerocounter architecture is recommended as a way to reducethe critical delay path. Alternative architectures for divisioncomputing should also be explored.Figure 4. Stem graph comparing the theoretical (blue) versus experimental(green) results.The MCCC algorithm used to test the circuit presents vul-nerability to both low sampling rates and precise localizationof sources positioned outside the range [60◦,120◦]. Increasingthe distance between microphones to increase the TDOArange beyond 500μs and reduce the required resolution is notdesirable; as distance between microphones is increased, onemust also increase the distance of the entire array to the source,or degradation in the algorithm’s performance might occur asa result of deviation from the ideal far-plane model assumedfor the MCCC’s derivation. For an application with movingsources, this is not recommended. Alternatively, additionalcomputing precision can help mitigate the angle issue, andcan be achieved by increasing the sample rate; should thisprove to be insufﬁcient, the determinant calculator’s precisionshould be increased by adding more mantissa bits to the baseword length, possibly by using the 32-bit standard IEEE formatinstead.REFERENCES[1] P. Julia´n, M. Favio, P. Mandolesi, A. Andreou, S. Shamma, E. Nebot,A. Chaco´n. 3D Gigascale Integrated Circuits for Nonlinear Computation,Filter and Fusion with Applications in Industrial Field Robotics.[2] A. Chacon-Rodriguez, F. Martin-Pirchio, S. San˜udo, and P. Julia´n. A lowpower integrated circuit for interaural time delay estimation without delaylines. Circuits and Systems Part II: Express Briefs, IEEE Transactions on,vol. 56, 2009, pp. 575-579.[3] A. Chacon-Rodriguez, P. Julian, and F. Masson. Fast and low powerintegrated circuit for impulsive sound localization using Kalman ﬁllterapproach. Electronics Letters, 46:533–534, April 2010.[4] R. Cerdas. Seleccio´n de un algoritmo de localizacio´n acu´stica para suuso en aplicaciones de robo´tica industrial. Lic. thesis, Dept. Electron.Eng., Instituto Tecnolo´gico de Costa Rica, Cartago, Costa Rica, 2012.[5] J. Benesty, J. Chen and Y. Huang. Microphone Array Signal Processing,chapter 9: DOA and TDOA estimation, pages 191–200. Springer, 1edition, 2008.[6] P. Julian, A. Andreou, L. Riddle, S. Shamma, D. Goldberg and G.Cauwenberghs. A Comparative Study of Sound Localization Algorithmsfor Energy Aware Sensor Network Nodes, in IEEE Trans. on Circuitsand Systems I: Regular Papers, vol.51, no.4, pp.640,648, April 2004,doi: 10.1109/TCSI.2004.826205[7] C.-L.Wey and C.-P.Wang. Design of a fast radix-4 SRT divider and itsVLSI implementation. In IEEE Proc.-Comput. Digit. Tech., IEEE. 1999.[8] M. P. Menezes, C. E. M. Pereira and L. M. Sato. IDM – A NewParallel Methodology to Calculate the Determinant of Matrices of theOrder n, with Computational Complexity O(n). In IEEE Latin AmericaTransactions, vol. 10:1. 2012.[9] UVM Introduction (2014, Oct. 6) [Online]. VLSI Encyclopedia. Avail-able: http://www.vlsiencyclopedia.com/2014/10/uvm-introduction.html

Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

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