This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment

Gustavo Ribeiro da Costa Alves

José Manuel Martins Ferreira

Marcelo Lubaszewski

Margrit Reni Krug

This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.info:eu-repo/semantics/publishedVersio

Krug, Margrit R.

Lubaszewski, Marcelo S.

Ferreira, Jose M.

Alves, Gustavo R.

Repositório Científico do Instituto Politécnico do Porto

Implementing a Self-Checking PROFIBUS SlaveMargrit Reni Krug*Marcelo Lubaszewski*José Manuel Martins Ferreira**Gustavo Ribeiro da Costa Alves**margrit@inf.ufrgs.br, luba@iee.ufrgs.brjmf@fe.up.pt, galves@def.isep.ipp.pt*PPGC – UFRGS – Instituto de InformáticaAv. Bento Gonçalves, 9500 – Campus do Vale – Bloco IVCaixa Postal 15064 – CEP 91501-970 Porto Alegre – RS - Brasil** Departamento de Engenharia Electrotécnica e de Computadores daFaculdade de Engenharia da Universidade do Porto - PortugalAbstractThis work presents the study andpreliminary results of the high levelimplementation of a self-checking Profibusslave. From an existing VHDL description ofthe device, a test strategy was studied andimplemented, so that the whole circuit hasembedded test structures capable to performat-speed test of the slave. In this paper, we showthe used test strategies and implementationresults achieved from a synthesis process in aFPGA environment.1 IntroductionIn a world of great and hardcompetition, it is mandatory for a company tosupply the best products and services to itscustomers. To make this task possible, a goodinformation system is crucial. A system capableto get and process data that come from factoryground is even more critical, since theseinformation contribute to taking severaldecisions, considering economical, technicialand safety factors. To accomplish thiscommunication between the equipments of afactory and the control system, fieldbuses areused. Due to the great importance of theinformation that is present in this sort of bus, itis necessary to guarantee the media reliabilityand avalability. A solution that presents a goodtradeoff between cost and efficiency is theintegrated self-test approach.Nowadays, the dimension of thesystems make it difficult the test process. Forthis problem, the solution has been the insertionof test structures into the circuit, rather than testthe complex system by external means[D&T97]. Since the fieldbuses are complexsystems used in crucial processes which claimfor security, the self-checking capability is ofgreat interest. In this work we address theproblems related to the self-checking design ofan entire slave block of a fieldbus, regarding thedescription language, time restrictions and areaoverhead.This paper presents in section 2 a briefdescription of industrial buses. In section 3, theProfibus struture, self-chek concept is discussed;in the section 4, test strategies for FSMs arestudied. Experimental results are presented insection 5. In section 6, an strategy to faulttolerant slave is presented, and, finally, ins ction 7, the conclusions and future works  aregiven. 2 Industrial BusesAn industrial bus, also known asfieldbus,  is a protocol for the communicationbetween automation and control equipments ofan industrial plant, such as sensors or actuatorsand a microprocessor.Several types of fieldbuses exist in themarket: Profibus [PRO98], Foundation Fieldbus[FOU96], CAN [CAN98], InterBus [INT98],etc. Each one has its characteristics andadvantages, but a standard protocol capable toprovide all industry requirements is notavaliable yet.The fieldbus came on as a solution forthe problem of  joining and operatinginstruments of factory ground. The mainrequirements for this protocol are: a) it shouldbe capable to operate instruments from differentmanufaturers having different features b) itshould work in a distributed system.This protocol implements sometechniques for safe communication, ensuring thetransmission of message packages (frames).Some test techniques, such as to verify whethera certain node of the net is active (that isanswering to requests and receivinginformation) are accomplished by most of theprotocols.However, the functionality of the bus,that is, if the protocol itself is meeting to itsrequirements, is not guaranteed. What isdetected now is if some device tied up in thefieldbus is not simply working. If the fieldbusitself fails, stopping its activities completely oreven presenting a random behavior, it does notexist a mechanism that comes to identify thefault, not even to signal the error.The behavior of permanent or randomfault in the fieldbus can cause considerablelosses, and possibly irreparable damages.Permanent faults occur in componentsaffected by mechanical rupture or some otherwaste phenomenon. Random faults are causedby disturbances of external signals, in general,due to radiations or electrical source floating.This paper aims at proporing a test techniquethat can detect those faults in a particularfieldbus described next, the Profibus.3 ProfibusThe Profibus is divided in amaster/slave structure. Master devices are calledactive elements, because any communicationrequest is accomplished through them. The slave Profibus is a passive elementof the architecture, because it can only answer torequests and never taking the initiative of acommunication. It is modeled using finite statemachines (FSM).A slave's Profibus FSM  consists onjust two states: offline and passive-idle. When astation is found in the offline state it is unable tocommunicate with any other station that is tiedup to the bus. This is due to the fact that theinitialization of the whole set of necessaryvariables to the communication process was notcorrectly done.After the initialization of the variables,the FSM  transitions from the offline state to thepassive-idle state, which represents theoperational state. The machine stays in this stateuntil  there is a restart request or till a fatal erroroccurs.In the passive-idle state the slavestation is permanently listening  to the messagespassing through the bus to check if they areaddressed for itself or if  they are broadcastmessages.4 The Self-Checking CapabilityIt is common knowledge that thesolution to test problems must be based on theadoption of a hierarchical and structuredstrategy, taken into account early in theintegrated circuit design. Furthermore, it isimportant that this same strategy can beemployed for design validation, manufacturing,maintenance and on-line tests, thus beingapplicable to all phases of a circuit’slifetime[LUB92].Existing off-line test techniques coverone part of  the test necessary for integratedcircuits and boards. These techniques, in theform of Built-In Self-Test (BIST) schemes[AGR93a],[AGR93b], have already reached animportant level of maturity regarding the faultcoverage, the surface overhead and the testapplication time.The other part of the tests necessary forcircuits and boards is related to the on-linetesting capability, a feature of great importancefor systems where poor functioning can, forexample, lead to a disaster.The self-checking circuitimplementation, for making on-line testingpossible, is based on the encoding of functionalblock outputs and on the verification of theseoutputs by specific checkers [CAR68].Thecircuit error indication is supplied by a globalchecker to the level immediately higher in thetest hierarchy (figure 1).FunctionalBlockEncoded OutputsCheckerError IndicationFigure 1 - A self-checking circuitThe goal to be self-checking circuits is oftencalled TSC (totally Self-Checking). The firsterroneous output of a functional block hasprovoke an error indication on its checkeroutputs. In [CAR68] is introduced the basicideas and Anderson [AND71] defined the TSCproperty for functional blocks and for checkers.Smith and Metze [SMI78] define SFS (StronglyFault Secure) circuits and Nicoladis et al[NIC84] defined SCD (Strongly Code Disjoit)checkers, wich are respectively the largestclasses of functional blocks and of checkersallowing the TSC goal to be ensured.In finite state machines, several faultscan occur, among them illegal and incorrectstate transition. The first one refers to atransition that is not specified in the machine. Inthe second one, the transition is specified in themachine, but it happened in an wrong time[ROC95]. Therefore it is very important toembed self-checking techniques in the slavecontrollers of the fieldbuses, to guarantee thatthe transition of the states happens in a safe way.5 FSM On-Line Test StrategyA typical fault in a FSM is a wrongstate transition, that may cause a transition to anew state that does not exist or that isincorrectly selected [LEE96]. An approachcapable to detect these single-state transitionfaults is a parity checker associated with theFSM as shown in figure 2 [SHE94]. Thistechnique was implemented in our Profibusslave.Figure 2 - Parity checkerIn this approach, a parity code isassociated with each state of the FSM, and aparity checker verifies the state transition todetect possible incorret behaviors. Thistechnique was presented in [SHE94], and itsmain advantage is that the circuit is capable tokeep working as a sequential circuit during test,avoiding scan propagation, very common in thiskind of logic. The state code is defined so thatfault masking is considered. The detailed codingmethod is presented in [SHE94] and it is basedon definitions of distinguishable machines[CHE92], [LEE76], [CHE90].This technique makes it possible theon-line test of the FSM, since it does notinterfere in the normal operation of the machine.6 Experimental ResultsThe slave block of the Profibus wasfirstly described using two VHDL [ALT95]modules. The first one represents the connectionof data of the frame level, called FHD3FRMand, the second one represents the level ofphysical connection, named  PHY_5.The technique of parity check wasimplemented in each one of the Profibus slavemachines.Table 1: Synthesis results for the original and self-checking  description the using parity checktechniqueBlock Device Number of LCs Percent ofdevice usedClock Frequency(MHz)Phy_5 EPF10K20RC240-4 179 15% 18.41Fhd3frm EPF10K20RC240-4 363 31% 10.35Phy_5 EPF10K20RC240-4 248 21% 14.81Fhd3frm EPF10K20RC240-4 511 44% 5.13CombinationallogicFlip-flopsParityCheckerOutputsInputsError indicationThe four descriptions of the Profibusslave, the original and the self-checking one,were synthesized using the ALTERA tool[ALT95]. Results in terms of number of logiccells, frequency of operation and device usedare shown in Table 1. In this table,  white rowsrepresent the original descriptions, and grayrows apply to the self-checking descriptions.With these results, it is possible to compare thecost of the insertion of self-checking structuresin a real application.The increase in terms of logic cells isof 40% and of 38,54%, respectively forFHD3FRM and PHY_5.In terms of clock frequency, thepenalties were also important. This decreasemay compromise the performance of someapplications. However, one should consider theadvantages of using a n on-line test technique toincrease the safety of the entire system.7 Evolving to Fault Tolerant SlaveAn other technique used to test FSMs iscalled Monitoring Machine. In this approach anauxiliary sequential circuit, called monitoringmachine, operates in lock-step with the mainmachine, such that any faulty in either of the twomachines is immediately detected [PAR96].The monitoring machine can be appliedto FSMs with pre-encoded states and facilitateson-line detection of errors, then  it also appliesdescription of slave PROFIBUS.We are now working on a proposed ofa different new implementation of themonitoring machine. In this version, themonitoring machine not only monitores the mainProfibus FSM but it is also capable to replacethis FSM in case of fault. The capability todistinguish wich of the two machines is faulty isachived by parity check, in much the same wayas described in the previous section.8 Conclusions and Future WorksThis work presented an implementationof a self-checking Profibus slave. Two modulesinside a VHDL description were identified,studied, and re-defined so that self-checkingstructures could be inserted. New VHDLdescriptions were implemented and synthesized,generating a complete at-speed self-checkingProfibus slave. Results in terms of areaoverhead and clock frequency for bothdescriptions were presented and compared.In the near future we intend to study thefault coverage for all blocks, to compare theimplementation of different self-checkingstrucutres to study the power consumption forthe self-checking implementation and to definethe best test schedule.Since the fault tolerance extension is anon going activity, the experimental referringresults of the implementation of the monitoringmachine technique will also be demonstrated infuture publications.9 References[AGR93a] AGRAWAL, V. D. , KIME, C.R.,SALUJA, K. K., A Tutorial on Built-InSelf_Test - Part 1: Principles. IEEE Design andTest of Computers, n. 10, v(1), 1993.[AGR93b] AGRAWAL, V. D., KIME, C. R.,SALUJA, K. K., A Tutorial on Built-InSelf_teste - Part2: Applications. IEEE Designand Test of  Computers, n. 10, v(2), 1993.[ALT95] ALTERA DATA BOOK  1995.Altera Corporation, march, 1995.[AND71] ANDERSON, D.A., Design of Self-Checking Digital Networks Usign CodingTechniques, CSL Univ. Of Illionois, Urbana,Report 527, September 1971.[CAN98] CAN- Controler Area Network -http//www.nrtt.demonco.co.ukl.[CAR68] CARTER, W.C. And SCHNEIDER,P. R., Design of Dynamically CheckerComputers, 4th IFIP Congress, Edinburgh,Scotland, v(2), pp. 878-883, 1968.[CHE90] Cheng, K.T.;Jou, J.Y, FunctionalTest Generation for Finite State Machines,International Test Conference, Proceedings...,1990, pp.162-168.[CHE92] Cheng, K.T.;Jou, J.Y., A FunctionalFault Model for Sequential Machines, IEEETransactions Computer-Aided Design, V(11),1992, pp. 1065-1073.[D&T97] Built-in Self-Test for Design. D&TRoundtable. IEEE Design and Test ofComputers, n. 3, v. 14, july-setember 1997.[FOU96] Foundation Fieldbus. TechnicalOverview, revision 1.0, September 1996.[INT98] INTERBUS,http://www.interbusclub.com, 1998[LEE76]Lee, S.C., Digital Circuits and LogicDesign, Prentice-Hall, Englewood Cliffs, N.J.,1976.[LEE96] LEE, D. And YANNAKAKIS, M.,Principles and Methods of Testing FiniteState Machines - A Survey . Procedings of  theIEEE, n. 8, v(84), August 1996.[LUB92] LUBASZEWSKI, M. AndCOURTOIS, B., On the Design of  Self-Checking Boundary Scannable Boards,International Test Conference, proceedings...,pp. 372-381, September, 1992.[NIC84] NICOLAIDIS, M., JANSCH, I. AndCOURTOIS, B., Strongly Code DisjointCheckers, Proc. Fault Tolerant Comp. Symp.,pp. 16-21, 1984.[PAR96] PAREKHJI, R. A., VENKATESH, G.And SHERLEKAR, S. D., MonitoringMachine Based Synthesis Technique forConcurrent Error Detection in Finite StateMachines. Journal of Eletronic Testing: Teoryand Applications, n. 8, pp. 179-201, 1996.[PRO98] PROFIBUS. Technical Overview.http://www.profibus.com, 1998.[SHE94] SHEU, M.l.; Lee, C.L.,Simplifying Sequential Circuit TestGeneration, IEEE Design and Test ofComputers, fall, 1994, pp.28-38.[SMI78] SMITH, J.E. And METZE, G.,Strongly Fault Secure Logic Networks, IEEETrans. On Computer, v(27), n 6, June 1978.[ROC95] ROCHET, R..; LEVEUGLE, R. AndSAUCIER, G. Efficiency Comparison ofSignature Monitoring Schemes for FSMs.International Conference ASP-DAC'95,CHDL'95 and VLSI'95, procedings...,Japan, 1995.

Implementing a Self- Checking PROFIBUS Slave

Scientific Repository of the Polytechnic Institute of Porto

English

Repositório Aberto da Universidade do Porto

Implementing a Self-Checking Profibus Slave

Open Repository of the University of Porto

Implementing a Self-Checking PROFIBUS Slave
Margrit Reni Krug*
Marcelo Lubaszewski*
José Manuel Martins Ferreira**
Gustavo Ribeiro da Costa Alves**
margrit@inf.ufrgs.br, luba@iee.ufrgs.br
jmf@fe.up.pt, galves@def.isep.ipp.pt
*PPGC – UFRGS – Instituto de Informática
Av. Bento Gonçalves, 9500 – Campus do Vale – Bloco IV
Caixa Postal 15064 – CEP 91501-970 Porto Alegre – RS - Brasil
** Departamento de Engenharia Electrotécnica e de Computadores da
Faculdade de Engenharia da Universidade do Porto - Portugal
Abstract
This work presents the study and
preliminary results of the high level
implementation of a self-checking Profibus
slave. From an existing VHDL description of
the device, a test strategy was studied and
implemented, so that the whole circuit has
embedded test structures capable to perform
at-speed test of the slave. In this paper, we show
the used test strategies and implementation
results achieved from a synthesis process in a
FPGA environment.
1 Introduction
In a world of great and hard
competition, it is mandatory for a company to
supply the best products and services to its
customers. To make this task possible, a good
information system is crucial. A system capable
to get and process data that come from factory
ground is even more critical, since these
information contribute to taking several
decisions, considering economical, technicial
and safety factors. To accomplish this
communication between the equipments of a
factory and the control system, fieldbuses are
used. Due to the great importance of the
information that is present in this sort of bus, it
is necessary to guarantee the media reliability
and avalability. A solution that presents a good
tradeoff between cost and efficiency is the
integrated self-test approach.
Nowadays, the dimension of the
systems make it difficult the test process. For
this problem, the solution has been the insertion
of test structures into the circuit, rather than test
the complex system by external means
[D&T97]. Since the fieldbuses are complex
systems used in crucial processes which claim
for security, the self-checking capability is of
great interest. In this work we address the
problems related to the self-checking design of
an entire slave block of a fieldbus, regarding the
description language, time restrictions and area
overhead.
This paper presents in section 2 a brief
description of industrial buses. In section 3, the
Profibus struture, self-chek concept is discussed;
in the section 4, test strategies for FSMs are
studied. Experimental results are presented in
section 5. In section 6, an strategy to fault
tolerant slave is presented, and, finally, in
section 7, the conclusions and future works  are
given.
 2 Industrial Buses
An industrial bus, also known as
fieldbus,  is a protocol for the communication
between automation and control equipments of
an industrial plant, such as sensors or actuators
and a microprocessor.
Several types of fieldbuses exist in the
market: Profibus [PRO98], Foundation Fieldbus
[FOU96], CAN [CAN98], InterBus [INT98],
etc. Each one has its characteristics and
advantages, but a standard protocol capable to
provide all industry requirements is not
avaliable yet.
The fieldbus came on as a solution for
the problem of  joining and operating
instruments of factory ground. The main
requirements for this protocol are: a) it should
be capable to operate instruments from different
manufaturers having different features b) it
should work in a distributed system.
This protocol implements some
techniques for safe communication, ensuring the
transmission of message packages (frames).
Some test techniques, such as to verify whether
a certain node of the net is active (that is
answering to requests and receiving
information) are accomplished by most of the
protocols.
However, the functionality of the bus,
that is, if the protocol itself is meeting to its
requirements, is not guaranteed. What is
detected now is if some device tied up in the
fieldbus is not simply working. If the fieldbus
itself fails, stopping its activities completely or
even presenting a random behavior, it does not
exist a mechanism that comes to identify the
fault, not even to signal the error.
The behavior of permanent or random
fault in the fieldbus can cause considerable
losses, and possibly irreparable damages.
Permanent faults occur in components
affected by mechanical rupture or some other
waste phenomenon. Random faults are caused
by disturbances of external signals, in general,
due to radiations or electrical source floating.
This paper aims at proporing a test technique
that can detect those faults in a particular
fieldbus described next, the Profibus.
3 Profibus
The Profibus is divided in a
master/slave structure. Master devices are called
active elements, because any communication
request is accomplished through them.
 The slave Profibus is a passive element
of the architecture, because it can only answer to
requests and never taking the initiative of a
communication. It is modeled using finite state
machines (FSM).
A slave's Profibus FSM  consists on
just two states: offline and passive-idle. When a
station is found in the offline state it is unable to
communicate with any other station that is tied
up to the bus. This is due to the fact that the
initialization of the whole set of necessary
variables to the communication process was not
correctly done.
After the initialization of the variables,
the FSM  transitions from the offline state to the
passive-idle state, which represents the
operational state. The machine stays in this state
until  there is a restart request or till a fatal error
occurs.
In the passive-idle state the slave
station is permanently listening  to the messages
passing through the bus to check if they are
addressed for itself or if  they are broadcast
messages.
4 The Self-Checking Capability
It is common knowledge that the
solution to test problems must be based on the
adoption of a hierarchical and structured
strategy, taken into account early in the
integrated circuit design. Furthermore, it is
important that this same strategy can be
employed for design validation, manufacturing,
maintenance and on-line tests, thus being
applicable to all phases of a circuit’s
lifetime[LUB92].
Existing off-line test techniques cover
one part of  the test necessary for integrated
circuits and boards. These techniques, in the
form of Built-In Self-Test (BIST) schemes
[AGR93a],[AGR93b], have already reached an
important level of maturity regarding the fault
coverage, the surface overhead and the test
application time.
The other part of the tests necessary for
circuits and boards is related to the on-line
testing capability, a feature of great importance
for systems where poor functioning can, for
example, lead to a disaster.
The self-checking circuit
implementation, for making on-line testing
possible, is based on the encoding of functional
block outputs and on the verification of these
outputs by specific checkers [CAR68].The
circuit error indication is supplied by a global
checker to the level immediately higher in the
test hierarchy (figure 1).
Functional
Block
Encoded Outputs
Checker
Error Indication
Figure 1 - A self-checking circuit
The goal to be self-checking circuits is often
called TSC (totally Self-Checking). The first
erroneous output of a functional block has
provoke an error indication on its checker
outputs. In [CAR68] is introduced the basic
ideas and Anderson [AND71] defined the TSC
property for functional blocks and for checkers.
Smith and Metze [SMI78] define SFS (Strongly
Fault Secure) circuits and Nicoladis et al
[NIC84] defined SCD (Strongly Code Disjoit)
checkers, wich are respectively the largest
classes of functional blocks and of checkers
allowing the TSC goal to be ensured.
In finite state machines, several faults
can occur, among them illegal and incorrect
state transition. The first one refers to a
transition that is not specified in the machine. In
the second one, the transition is specified in the
machine, but it happened in an wrong time
[ROC95]. Therefore it is very important to
embed self-checking techniques in the slave
controllers of the fieldbuses, to guarantee that
the transition of the states happens in a safe way.
5 FSM On-Line Test Strategy
A typical fault in a FSM is a wrong
state transition, that may cause a transition to a
new state that does not exist or that is
incorrectly selected [LEE96]. An approach
capable to detect these single-state transition
faults is a parity checker associated with the
FSM as shown in figure 2 [SHE94]. This
technique was implemented in our Profibus
slave.
Figure 2 - Parity checker
In this approach, a parity code is
associated with each state of the FSM, and a
parity checker verifies the state transition to
detect possible incorret behaviors. This
technique was presented in [SHE94], and its
main advantage is that the circuit is capable to
keep working as a sequential circuit during test,
avoiding scan propagation, very common in this
kind of logic. The state code is defined so that
fault masking is considered. The detailed coding
method is presented in [SHE94] and it is based
on definitions of distinguishable machines
[CHE92], [LEE76], [CHE90].
This technique makes it possible the
on-line test of the FSM, since it does not
interfere in the normal operation of the machine.
6 Experimental Results
The slave block of the Profibus was
firstly described using two VHDL [ALT95]
modules. The first one represents the connection
of data of the frame level, called FHD3FRM
and, the second one represents the level of
physical connection, named  PHY_5.
The technique of parity check was
implemented in each one of the Profibus slave
machines.
Table 1: Synthesis results for the original and self-checking  description the using parity check
technique
Block Device Number of LCs Percent of
device used
Clock Frequency
(MHz)
Phy_5 EPF10K20RC240-4 179 15% 18.41
Fhd3frm EPF10K20RC240-4 363 31% 10.35
Phy_5 EPF10K20RC240-4 248 21% 14.81
Fhd3frm EPF10K20RC240-4 511 44% 5.13
Combinational
logic
Flip-flops
Parity
Checker
OutputsInputs
Error indication
The four descriptions of the Profibus
slave, the original and the self-checking one,
were synthesized using the ALTERA tool
[ALT95]. Results in terms of number of logic
cells, frequency of operation and device used
are shown in Table 1. In this table,  white rows
represent the original descriptions, and gray
rows apply to the self-checking descriptions.
With these results, it is possible to compare the
cost of the insertion of self-checking structures
in a real application.
The increase in terms of logic cells is
of 40% and of 38,54%, respectively for
FHD3FRM and PHY_5.
In terms of clock frequency, the
penalties were also important. This decrease
may compromise the performance of some
applications. However, one should consider the
advantages of using a n on-line test technique to
increase the safety of the entire system.
7 Evolving to Fault Tolerant Slave
An other technique used to test FSMs is
called Monitoring Machine. In this approach an
auxiliary sequential circuit, called monitoring
machine, operates in lock-step with the main
machine, such that any faulty in either of the two
machines is immediately detected [PAR96].
The monitoring machine can be applied
to FSMs with pre-encoded states and facilitates
on-line detection of errors, then  it also applies
description of slave PROFIBUS.
We are now working on a proposed of
a different new implementation of the
monitoring machine. In this version, the
monitoring machine not only monitores the main
Profibus FSM but it is also capable to replace
this FSM in case of fault. The capability to
distinguish wich of the two machines is faulty is
achived by parity check, in much the same way
as described in the previous section.
8 Conclusions and Future Works
This work presented an implementation
of a self-checking Profibus slave. Two modules
inside a VHDL description were identified,
studied, and re-defined so that self-checking
structures could be inserted. New VHDL
descriptions were implemented and synthesized,
generating a complete at-speed self-checking
Profibus slave. Results in terms of area
overhead and clock frequency for both
descriptions were presented and compared.
In the near future we intend to study the
fault coverage for all blocks, to compare the
implementation of different self-checking
strucutres to study the power consumption for
the self-checking implementation and to define
the best test schedule.
Since the fault tolerance extension is an
on going activity, the experimental referring
results of the implementation of the monitoring
machine technique will also be demonstrated in
future publications.
9 References
[AGR93a] AGRAWAL, V. D. , KIME, C.R.,
SALUJA, K. K., A Tutorial on Built-In
Self_Test - Part 1: Principles. IEEE Design and
Test of Computers, n. 10, v(1), 1993.
[AGR93b] AGRAWAL, V. D., KIME, C. R.,
SALUJA, K. K., A Tutorial on Built-In
Self_teste - Part2: Applications. IEEE Design
and Test of  Computers, n. 10, v(2), 1993.
[ALT95] ALTERA DATA BOOK 1995.
Altera Corporation, march, 1995.
[AND71] ANDERSON, D.A., Design of Self-
Checking Digital Networks Usign Coding
Techniques, CSL Univ. Of Illionois, Urbana,
Report 527, September 1971.
[CAN98] CAN- Controler Area Network -
http//www.nrtt.demonco.co.ukl.
[CAR68] CARTER, W.C. And SCHNEIDER,
P. R., Design of Dynamically Checker
Computers, 4th IFIP Congress, Edinburgh,
Scotland, v(2), pp. 878-883, 1968.
[CHE90] Cheng, K.T.;Jou, J.Y, Functional
Test Generation for Finite State Machines,
International Test Conference, Proceedings...,
1990, pp.162-168.
[CHE92] Cheng, K.T.;Jou, J.Y., A Functional
Fault Model for Sequential Machines, IEEE
Transactions Computer-Aided Design, V(11),
1992, pp. 1065-1073.
[D&T97] Built-in Self-Test for Design. D&T
Roundtable. IEEE Design and Test of
Computers, n. 3, v. 14, july-setember 1997.
[FOU96] Foundation Fieldbus. Technical
Overview, revision 1.0, September 1996.
[INT98] INTERBUS,
http://www.interbusclub.com, 1998
[LEE76]Lee, S.C., Digital Circuits and Logic
Design, Prentice-Hall, Englewood Cliffs, N.J.,
1976.
[LEE96] LEE, D. And YANNAKAKIS, M.,
Principles and Methods of Testing Finite
State Machines - A Survey . Procedings of  the
IEEE, n. 8, v(84), August 1996.
[LUB92] LUBASZEWSKI, M. And
COURTOIS, B., On the Design of  Self-
Checking Boundary Scannable Boards,
International Test Conference, proceedings...,
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Implementing a Self-Checking Profibus Slave

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