An elegant breadboard model of the LISA phasemeter is currently under
development by a Danish-German consortium. The breadboard is build in the frame
of an ESA technology development activity to demonstrate the feasibility and
readiness of the LISA metrology baseline architecture. This article gives an
overview about the breadboard design and its components, including the
distribution of key functionalities.Comment: 5 pages, 3 figures, published in ASP Conference Series, Vol. 467, 9th
  LISA Symposium (2012), pp 271-27

Barke, Simon

Bykov, Ioury

Danzmann, Karsten

Enggaard, Anders

Esteban, Juan Jose

Gerberding, Oliver

Gianolio, Alberto

Hansen, Torben Vendt

Heinzel, Gerhard

Hornstrup, Allan

Jennrich, Oliver

Kullmann, Joachim

Pedersen, Søren Møller

Rasmussen, Torben

Reiche, Jens

Sodnik, Zoran

Suess, Martin

English

arXiv

An elegant breadboard model of the LISA phasemeter is currently under development by a Danish-German consortium. The breadboard is build in the frame of an ESA technology development activity to demonstrate the feasibility and readiness of the LISA metrology baseline architecture. This article gives an overview about the breadboard design and its components, including the distribution of key functionalities

Gerberding, O.

Barke, S.

Bykov, I.

Danzmann, K.

Enggaard, A.

Esteban, J.

Gianolio, A.

Hansen, T.

Heinzel, G.

Hornstrup, A.

Jennrich, O.

Kullmann, J.

Pedersen, S.

Rasmussen, T.

Reiche, J.

Sodnik, Z.

Suess, M.

MPG.PuRe

arXiv:1208.6418v1  [astro-ph.IM]  31 Aug 2012**Volume Title**ASP Conference Series, Vol. **Volume Number****Author**c©2012 Astronomical Society of the PacificBreadboard model of the LISA phasemeterO. Gerberding1, S. Barke1, I. Bykov1, K. Danzmann1, A. Enggaard2,J.J. Esteban1, A. Gianolio3, T.V. Hansen2, G. Heinzel1, A. Hornstrup4,O. Jennrich3, J. Kullmann1, S.M. Pedersen4, T. Rasmussen2, J. Reiche1,Z. Sodnik3 and M. Suess31 Max-Planck Institute for Gravitational Physics (Albert Einstein Institute) andInstitute for Gravitational Physics, Leibniz University Hannover, Callinstrasse38, 30167 Hannover, Germany2 Axcon ApS, Diplomvej 381, DK-2800 Kgs. Lyngby, Denmark3 European Space Research and Technology Centre, European Space Agency,Keplerlaan 1, 2200 AG Noordwijk, The Netherlands4 DTU Space, National Space Institute, The Technical University of Denmark,Elektrovej 327, DK-2800 Kgs. Lyngby, DenmarkAbstract. An elegant breadboard model of the LISA phasemeter is currently u derdevelopment by a Danish-German consortium. The breadboardis build in the frame ofan ESA technology development activity to demonstrate the feasibility and readinessof the LISA metrology baseline architecture. This article gives an overview about thebreadboard design and its components, including the distribution of key functionalities.1. IntroductionOne of the main building blocks of the LISA metrology system is the frequency dis-tribution and phase measurement system (phasemeter) (Jennrich (2009)). We are cur-rently developing a breadboard model (BB) of the LISA phasemet r in the frame ofan ESA technology development activity. The BB will be used to test and validate thefunctionality and performance as required for the LISA metrology system. We willdemonstrate the technological readiness and evaluate a future space qualification. Theactivity is performed by a consortium composed of the National Space Insitute of theDanish Technical University (DTU Space), the Danish industry partner Axcon ApS inCopenhagen, and the Max-Planck Institute for Gravitational Physics, Albert-EinsteinInstitute (AEI) in Hannover.This activity is part of a world wide effort to develop and demonstrate the metrol-ogy concepts for the LISA interferometry (Spero et al. (2011); Mitryk et al. (2010);Heinzel et al. (2011)). Tests of the full LISA metrology baselin architecture can beperformed with the BB. This is achieved by combining the capabilities for phase mea-surements, Time-Delay interferometry, clocktone transfer, testmass readout, laser con-trol and inter spacecraft communications into a single device.The BB (figure 1 shows a schematic layout) consists of four types of modules,each containing different functionalities. The main module is the central part of the12 O. Gerberding et al.FFT FPGABRIDGEFPGACPUfrequencygenerationsystempilot tonedistributionslot2ADCFPGAlocal power supplyADCanalog frontendSMA SMA SMA SMASMAPTSMAPTSMAPTSMAPTSMAPTSMAPTSMAPTslot3slot6slot5DACFPGAlocal power supplyDACsanalogbackendSMA SMA SMA SMASMASMASMAmain moduleADC moduleDAC moduleclock moduleinterfacesDDR2FlashDDR2analogpower supplydigitalpowersupplyFigure 1. Schematic overview of the LISA phasemeter Breadbord model. Themain module carries up to five ADC modules, one DAC module and one clock mod-ule. The pilot tone distribution is located in the middle of the BB to shorten itscritical path. The FPGAs generating most of the heat in the system are located at theoutside, allowing effective cooling and protection of the cricital analog circuits.BB and connects to all other modules and the outside world. One ADC module han-dles the readout of up to four analog input channels and one BBcan carry up to fivemodules, leading to a total number of 20 input channels. The clock module containsthe frequency generation system and the pilot tone distribution. Furthermore each BBcarries a DAC module, which produces all analog output signals of the phasemeter. Themodular approach was chosen to allow independent testing and optimization of criticalcomponents and to reduce production cost and risk. In the following we will give adetailed overview of each module.2. ADC moduleThe actual measurement of the incoming signals is implemented on this module. Themeasurement chain consists of an analog frontend stage, preparing the signal for digi-tisation, a fast ADC, sampling with 80 MHz, and a FPGA containing the digital sys-tem processing. This includes the readout of the signal phase (Shaddock et al. (2006);Bykov et al. (2009)), the readout of inter-satellite ranging and communications (Esteban et al.(2011); Sutton et al. (2010)) and the readout of the clock tone sidebands (Heinzel et al.(2011)).Breadboard model of the LISA phasemeter 32.1. Analog frontendThe analog frontend includes a gain stage, an anti-aliasingfilter, an addition of a pilottone for ADC jitter correction and some signal conditioningfor the ADC. Preinvestiga-tions have shown that this is one of the most critical components of the BB, thereforewe included the possibiliy of exchanging the frontend by soldering an alternative PCBboard on top.2.2. Digital signal processingThe actual phase readout of the MHz signals is performed by the use of specificlydesigned phase-locked loops (PLL). Each type of signal tone(sci nce, pilot and side-band) is tracked seperately and the computed signals are decimat d, downsampled andstreamed to the further processing chain. The decimation rates and interface speeds aredesigned according to the bandwidth requirements of a potential DFACS system andthe implementation of a digital laser lock. The readout of the inter-satellite ranging isperformed in two delay-locked loops (DLL), which are tracking the local and remotepseudo-random noise (PRN) codes. The received delays and data are also transmittedto the CPU for storage and further processing.3. DAC ModuleThe BB will also generate analog signals, which is done on theDAC module. It con-tains an FPGA, allowing to implement low-level computations and interfacing digitalto analog converters and an analog signal conditioning, including additional gains andfiltering. One of the main functionality is the generation and data encoding of the PRNsignals, necessary for the intersatellite communication and data transfer. We have im-plemented three PRN outputs, to allow tests in a three laser setup. The other function-ality is the generation of control signals for local lasers,to establish the LISA lockingscheme. This includes the generation of four analog signalsfor controlling up to twoslave lasers and the implementation of control algorithms in the FPGAs. This can ei-ther be the digital equivalent to an analog frequency offset phase-lock (Diekmann et al.(2009); Cruz et al. (2006)), or the implementation of more complex algorithms, likearm-locking (Yu et al. (2011)).4. Clock ModuleThe clock module supplies the system clock and the pilot tonethe BB. It either gen-erates or receives two GHz signals with a fixed phase relationto the pilot tone, whichare used for the clock tone transfer. It consists of an analogsignal chain and is dividedinto the generation of signals in the Frequency generation section and the distributionof the pilot tone to the ADC modules. The system sampling clock is distributed viathe PCB board, while the pilot tone is seperated, to ensure its stability. The positioningof the clock module allows to optimize the signal distribution and allows to decreasethe influence of strong heat dissipation by the FPGAs. Similar to the analog frontendof the ADC modules this component is a critical factor of the BB. It contains varioustesting possibilities to ensure the required funtionalityand performance, as well as itsown stabilised power supply.4 O. Gerberding et al.BRIDGEFPGAFFT FPGACPUADCFPGAADCFPGAADCFPGAADCFPGAADCFPGADACFPGAADC timeseries/debug dataFFT results/debug datalaser control /data to other SCscience/dataDFACS/PCsciencereferenceauxilliarymain moduleBRIDGE FPGACPUFFT FPGAτsyncτsyncτsyncADC moduleADC FPGAbu!er  1:8tickADC moduleADC moduleADC moduleADC moduleDAC moduleFigure 2. (left) System communication structure. All communication is routedthrough the bridge FPGA, with the exception of the highspeeddata for the FFTFPGA. (right) Time tick distribution in the system via the bridge FPGA. All delaysare matched, as well as the clock signals (not shown here), toallow a system widehardware synchronization.5. Main ModuleBesides the function as baseplate and power supply, the mainodule contains centralparts of the functionality. A separate ”Bridge FPGA” is handli g the system communi-cation between the different FPGAs and a CPU, which is controlling the BB. A sketchof this is shown in figure 2 (left). The CPU is also performing parts of the digitalsignal processing, data storage and the potential communication to a DFACS simula-tor. In addition the main board contains another FPGA, whichis dedicated to performFast-Fourier Transforms of the incoming signal for lock acquisition procedures.5.1. Bridge FPGAThe bridge FPGA is the central switch for most communications a d is directly inter-faced to the CPU, sending data to it and distributing commands from it to the respectivesubmodules. For synchronising the various FPGAs system a tie tick can be triggeredat the bridge (see figure 2, (right)). This tick is sent to all FPGAs with the same timedelay, also back to the bridge. This allows to synchronize clock counters in all systems,as well as any other action to a single clockcycle. Together with the pilot tone correc-tion it forms the basis for meeting the stringent LISA timingrequirements necessaryfor implementing TDI and clock noise corrections.5.2. FFT FPGATo ensure a maximum acquisition performance the FFT FPGA canperform four fulldutycycle FFTs with the complete ADC timeseries of an ADC module, transmitted bydedicated fast interfaces. It also hosts a peak detection algorithm and the possibilityof storing a fullspeed datastream into dedicated DDR RAM. This stream is then readBreadboard model of the LISA phasemeter 5out via the CPU and can be used to perform debugging and signalanalysis for shortsequences at the full sampling rate.5.3. CPUThe CPU will control the BB, perform housekeeping procedures, change operatingmodes and ensure synchronisation of all submodules. It is also performing several tasksfor the digital signal processing. This includes a final datafil ering and decimationto prepare the data for the DFACS system or for transmission to ground. The CPUis also handling the data storage and the preperation of datafor the inter spacecraftcommunication.6. OutlookAfter the assembly of the BB, we will perform functionality and performance testswith electronic signals. The performance goals of all subsystems are calculated fromthe requirement of 1 pm/√Hz in the range of 0.1 mHz and 1 Hz with the standard noiseshape. Future steps are tests in LISA like optical setups andthe evaluation of a designfor space qualification.Acknowledgments. This work was funded by the European Space Agency (ESA)as part of the technology development for LISA. The authors greatfully acknowledgethe support by the International Max-Planck Research School for Gravitational WaveAstronomy (IMPRS-GW), by QUEST (Centre for Quantum Engineering and Space-Time Research) and by Deutsches Zentrum für Luft-und Raumfhrt (DLR) (reference50 OQ 0601).ReferencesBykov, I., Esteban, J. J., Garcı̀a Marı̀n, A. F., Heinzel, G., & Danzmann, K. 2009, Journal ofPhysics: Conference Series, 154, 012017Cruz, R. J., Thorpe, J. I., Preston, A., Delgadillo, R., Hartmann, M., Mitryk, S., Worley, A.,Boothe, G., Guntaka, S. R., Klimenko, S., Tanner, D. B., & Mueller, G. 2006, Classicaland Quantum Gravity, 23, S751Diekmann, C., Steier, F., Sheard, B., Heinzel, G., & Danzmann, K. 2009, Journal of Physics:Conference Series, 154, 012020Esteban, J. J., Garcia Marin, A. F., Barke, S., Peinado, A. M., Guzman Cervantes, F., Bykov, I.,Heinzel, G., & Danzmann, K. 2011, Optics Express, 19, 15937Heinzel, G., Esteban, J. J., Barke, S., Otto, M., Wang, Y., Garcia Marin, A. F., & Danzmann, K.2011, Classical and Quantum Gravity, 28, 094008Jennrich, O. 2009, Classical and Quantum Gravity, 26, 153001Mitryk, S., Wand, V., & Mueller, G. 2010, Classical and Quantum Gravity, 27, 084012Shaddock, D., Ware, B., Halverson, P., Spero, R. E., & Klipstein, B. 2006, AIP Conf. Proc.,873, 689Spero, R., Bachman, B., de Vine, G., Dickson, J., Klipstein,W., Ozawa, T., McKenzie, K.,Shaddock, D., Robison, D., Sutton, A., & Ware, B. 2011, Classical and Quantum Grav-ity, 28, 094007Sutton, A., McKenzie, K., Ware, B., & Shaddock, D. 2010, Optics Express, 18, 20759Yu, Y., Mitryk, S. J., & Mueller, G. 2011, Classical and Quantum Gravity, 28, 094009

Breadboard model of the LISA phasemeter

Breadboard model of the LISA phasemeter

Abstract

Similar works

Full text

Available Versions

MPG.PuRe

MPG.PuRe