制度:新 ; 報告番号:甲2876号 ; 学位の種類:博士(工学) ; 授与年月日:2009/9/15 ; 早大学位記番号:新510

Liu Qin

English

制度:新 ; 報告番号:甲2876号 ; 学位の種類:博士(工学) ; 授与年月日:2009/9/15 ; 早大学位記番号:新5103textthesi

Liu, Qin

31988

Waseda University Repository

Low-complexity video compression algorithm and video encoder LSI design

DSpace at Waseda University

  早稲田大学大学院情報生産システム研究科     博 士 論 文 概 要        論  文  題  目    Low-Complexity Video Compression Algorithm and Video Encoder LSI Design        申  請  者  劉 欽  LIU, Qin    情報生産システム工学専攻  超並列 LSI 研究   2009 年 4 月   2 D ig i ta l  v ideo  i s  becoming  to  a  ub iqui tous  and  essent ia l  component  in  da i ly  l i f e .  Owing  to  l imi ted  network  bandwidth  and  hard  d isk  s torage  capac i ty,  v ideo  compress ion  becomes  to  a  c r i t i ca l  i s sue  in  the  modern  wor ld .  As  o f  2009 ,  H .264 ,  the  la tes t  b l ock -or iented  commot ion  compensat ion  based  codec  s tandard ,  has  been  deve loped  by  ITU-T  VCEG together  wi th  ISO/ IEC MPEG.  The  H.264 /AVC i s  t o  c reate  a  s tandard  capab le  o f  prov id ing  good  v ideo  qual i ty  a t  substant ia l ly  l ower  b i t  ra tes  than  prev ious  s tandards .  However,  the  cos t  i s  huge - increas ing  complex i ty,  espec ia l ly  incurs  the  d i sp leasure  o f  h igh  power  consumption  f or  the  v ideo  encoder  LSI  des ign .    Thus ,  two  key  prob lems  for  v ideo  encoder  des ign  come  to  us :   1 .  Low Computat ion  Complexi ty  A lgor i thm  2 .  Low Power  Hardware  Implementat i on     For  the  f i r s t  prob lem,  the  key  complex i ty - intens ive  par t  f o r  H .264  i s  the  b lock -match ing -a lgor i thm (BMA)  based  mot ion  es t imat ion  (ME)  par t ,  which  i s  the  process  o f  de termin ing  mot ion  vec tors  that  descr ibe  the  t rans format ion  be tween  success ive  f rames  to  remove  the  tempora l  redundancy.  Convent iona l  fu l l  search  method  in  mot ion  es t imat ion ,  searches  each  search  candidate  po int  sequent ia l ly.  A l though  th is  method  can  ge t  the  bes t  mot ion  vec tor,  the  ca l cu la t i on  burden  i s  huge .  Espec ia l ly  fo r  the  H.264 ,  i t  adopts  some  e f f e c t ive  fea tures  such  as  the  var iab le  b lo ck  s i zed  mot ion  es t imat ion  (VBSME)  and mul t ip le  re fe rence  f rame  (MRF)  to  improve  the  v ideo  compress ion  qua l i ty.  Thus ,  fu l l  search  has  to  ca l cu la te  a l l  the  search  candidate  po ints  in  each  search  window for  a l l  the  7  types  b lock  s i zes  and  a l l  re fe rence  f rames  (5  re ference  f rames  in  common case ) .   In  th is  d isser ta t i on ,  f our  ser ies  o f  a lgor i thms  are  proposed  to  ach ieve  l ow-complex i ty  f o r  v ideo  encoder,  which  are  mainly  f o r  ME module .  At  f i r s t ,  edge  b lock  detec t ion  and  mot ion  vec tor  in format ion  based  fas t  ME a lgor i thm i s  a imed  to  adapt ive ly  reduce  redundant  search  range ,  redundant  re ference  f rame ,  and  redundant  b lock  matching  operat ion .  Second ly,  two -s tep  c ross -d iamond fas t  ME a lgor i thm i s  fo cused  on  search  candidate  reduct ion  wi th  adapt ive  search  pat tern .  Th ird ly,  ra te -d i s tor t i on  opt imizat ion  based  sk ip  mode  ear ly  de tec t i on  a lgor i thm i s  des igned  f or  ear ly  terminat ing  ME module  wi th  neg l ig ib le  v ideo  qual i ty  l oss .  Fourth ly,  A l l -Zero  B lock  (AZB)  ear ly  detec t i on  a lgor i thms  are  proposed  to  reduce  the  t rans format ion  and  quant i zat ion ’s  computat ion  complex i ty,  which  are  a l so  he lp fu l  t o  ear ly  te rminate  the  ME process .  For  the  second  prob lem,  d i f f e rent  hardware  arch i tec tures  are  des igned  fo r  d i f f e rent  so f tware  a lgor i thms  to  ach ieve  l ow power.  Owing  to  the  most   3 f requent  operat ion ,  sum o f  abso lute  d i f f e rences  (SAD) ,  a  SIMD-SAD based ME processor  fo r  ASIP v ideo  encoder  i s  proposed ,  which  can  benef i t  f rom proposed  low-complex i ty  fas t  ME a lgor i thms to  acce lerate  v ideo  encoder.   Thus ,  the  organizat i on  o f  th is  d i sser ta t ion  i s  d iv ided  in to  f our  par ts .  Background  introduct ion  i s  presented  a t  f i r s t  [Chapter  1 ] .  The  body  o f  th is  d i sser tat ion  i s  composed  o f  two  par ts :  l ow-complex i ty  so f tware  a lgor i thm des ign  f or  v ideo  encoder  [Chapter  2 ,  3 ,  4 ,  5 ]  and  the  l ow-powe r  hardware  LSI  des ign  for  v ideo  encoder  [Chapter  6 ] .  Conc lus ion  i s  drawn in  the  f our th  par t  [Chapter  7 ] .    Chapter  1   [ In troduct ion ]    Some  background  knowledge  f o r  v ideo  compress ion  i s  in t roduced .  The  a lgor i thm f l ow and  LSI  arch i tec ture  fo r  the  la tes t  H .264  encoder  are  expla ined  in  de ta i l s ,  e spec ia l ly  f o r  the  key  computat ion - intens ive  mot ion  es t imat ion  par t .  Our  contr ibut ions  are  a l so  presented  in  th is  chapter.    Chapter  2   [Edge  B lock  Detec t i on  and  Mo t ion  Vec tor  In format ion  based  Fast  ME Algor i thm]  Mathemat i ca l  ana lys i s  revea ls  that  the  a l ias ing  prob lem o f  subsampl ing  a lgor i thm comes  f rom h igh  f requency  s ignal  components .  Moreover,  h igh  f requency  s ignal  components  are  a l so  the  main  i ssues  that  make  MRF a lgor i thm essent ia l .  A p i c ture  be ing  r i ch  o f  t ex ture  must  conta in  l o t s  o f  h igh  f requency  s igna ls .  So  based  on  these  mathemat i ca l  inves t igat ions ,  two  fas t  VBSME a lgor i thms  are  proposed  in  th is  chapter,  namely  edge  b lock  detec t i on  based  subsampl ing  method  and  mot ion  vec tor  based  MRF ear ly  te rminat ion  a lgor i thm.  Exper iments  show that  s t rong  corre la t ion  ex i s t s  among  the  mot ion  vec tors  o f  those  b locks  be long ing  to  the  same  macrob lock .  Through  exp lo i t ing  th i s  f eature ,  a  dynamica l ly  ad justment  o f  the  search  ranges  o f  in teger  mot ion  es t i mat ion  i s  proposed  in  th i s  chapter.  Combing  our  proposed  a lgor i thms  wi th  UMHS a lmost  saves  96%-98% Integer  Mot ion  Est imat ion  ( IME)  t ime  compared  to  the  exhaust ive  search  a lgor i thm.  The  induced  cod ing  qual i ty  l oss  i s  l e ss  than  0 .8% b i t rate  increase  or  0 .04  db  PSNR dec l ine  on  average .    Chapter  3   [Two-Step  Cross -Diamond  Fast  ME Algor i thm]  A fas t  ME search  a lgor i thm based  on  a  two -s tep  coarse  to  f ine  s t rategy  by  c ross  and  d iamond  search  pat terns  i s  proposed .  And  mot ion  vec tor  pred i c tors  and  ear ly  terminat ion  technique  are  combined  to  reduce  search  po ints .  The  exper iment  resul t s  show that  th i s  fas t  search  a lgor i thm has  reduced  60% search  po ints  and  20% mot ion  es t imat ion  t ime  compared  wi th  UMHS a lgor i thm,  wi th  on ly  l ess  than  0 .04dB loss  in  the  v ideo  qual i ty.   4 Chapter  4   [RDO based  Sk ip  Mode  Ear ly  De tec t i on  Algor i thm]  In  th i s  paper,  a  theore t i ca l  analys is  i s  per formed  fo r  ra te -d i s tor t ion  opt imizat ion  (RDO)  a lgor i thm for  sk ip  mode .  As  a  resu l t ,  a  RDO based  sk ip  mode  ear ly  de tec t ion  a lgor i thm i s  der ived  to  reduce  ME complex i ty.  Exper imenta l  resul t s  show that  the  proposed  a lgor i thm achieves  major  improvement  o f  computat ion  reduct ion  in  the  range  f rom 12 .1% to  72 .9%.     Chapter   5   [4x4  and  8x8  A l l -Zero  B locks  Ear ly  Detec t i on  A lgor i thms]  Af ter  t rans form and  quant izat ion ,  i f  a l l  the  coe f f i c i ents  o f  the  b lock ' s  res idue  data  are  zero ,  th i s  b lock  i s  ca l led  a l l - zero  b lock  (AZB) .  Prov ided  that  an  AZB can  be  detec ted  ear ly,  the  process  o f  t rans form and  quant izat ion  on  an  AZB can  be  sk ipped ,  which  reduces  s igni f i cant  redundant  computat ions .  In  th i s  chapter,  a  theore t i ca l  ana lys i s  i s  per formed  for  the  su f f i c i ent  cond i t io n  f or  AZB detec t i on .  As  a  resu l t ,  a  par t ia l  sum o f  abso lute  d i f fe rence  (SAD)  based  4x4  AZB detec t i on  a lgor i thm i s  der ived .  Furthermore ,  a  quant izat i on  parameter  (QP)  or i ented  8x8  AZB detec t ion  a lgor i thm is  proposed  accord ing  to  the  AZB 's  s ta t i s t i ca l  analys i s .  Moreover,  SATD based  4x4  and  8x8  AZB detec t i on  a lgor i thms  are  a lso  proposed  in  th is  chapter.  Exper imenta l  resu l ts  show that  the  proposed  a lgor i thms  outper form the  prev ious  methods  and  achieve  major  improvement  o f  computat ion  reduct ion  in  the  range  f rom 6 .7% to  42 .3% for  4x4  b locks ,  f rom 0 .24% to  79 .48% for  8x8  b locks .    Chapter  6   [Fast  ME Algor i thms  based  ASIP Video  Encoder  Des ign ]  A low-power  app l i ca t i on-spec i f i c  ME-MC processor  in  v ideo  encoder  i s  proposed .  Edge  b lock  Detec t i on  and  SAD Calcu lat i on  ins t ruc t i ons  have  been  des igned  and  SIMD method  i s  u t i l i zed  to  acce lerate  them.  As  a  resul t ,  our  proposed  ASIP arch i tec ture  can  save  95% ins truc t ion  f or  most  computat ion  in tens ive  SAD part ,  and  about  60% power  reduct ion  can  be  achieved  wi th  our  proposed  ME processor.     Chapter  7   [Conc lus ion ]  Conc lus ion  fo r  th i s  d i sser tat i on  i s  drawn in  las t  chapter.     To  sum i t  up ,  a  f eas ib le  l ow  complex i ty  so lut ion  f o r  v ideo  encoder  i s  proposed  in  th i s  d i sser ta t ion ,  which  i s  based  on  proposed  fas t  mot ion  es t imat ion  a lgor i thms  and  ASIP ME processor.  Proposed  fas t  mot ion  es t imat ion  a lgor i thms  can  reduce  complex i ty  huge ly  ( computat ion  reduct ion  f rom 35% to  73%)  wi th  no  s ign i f i cant  v ideo  qua l i ty  l o ss ,  whi le  ASIP ME can  acce lerate  a lgor i thms  in  hardware  implementat i on  (60% power  reduct ion ) .  As  a  conc lus ion ,  our  proposed  so lut ion  f o r  v ideo  encoder  ach ieved  power  reduct ion  f rom 75% to  89% for  d i f f e rence  v ideo  sequence .     

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Low-complexity video compression algorithm and video encoder LSI design

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