A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.Fil: Chacón-Rodríguez, A.. Universidad de Mar del Plata. Laboratorio de Componentes Electrónicos; ArgentinaFil: Martín-Pirchio, F. N.. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentin

Chacón-Rodríguez, A.

Julian, Pedro Marcelo

Mandolesi, Pablo Sergio

Martín-Pirchio, F. N.

English

CONICET Digital

Latin American Applied Research 37:41-45 (2007) 41 A VERILOG HDL DIGITAL ARCHITECTURE FOR DELAY CALCULATION  A. CHACÓN-RODRÍGUEZ†, F. N. MARTÍN-PIRCHIO‡, P. JULIÁN‡§ and P. S. MANDOLESI‡ † Laboratorio de Componentes Electrónicos, Universidad Nacional de Mar del Plata, Mar del Plata, Argentina,  on leave from Instituto Tecnológico de Costa Rica. achacon@fi.mdp.edu.ar ‡  Departamento de Ingeniería Eléctrica y Computadores, Universidad Nacional del Sur, Bahía Blanca, Argentina §Consejo Nacional de Investigaciones Científicas y Técnicas-(CONICET)  fmartinpirchio@uns.edu.ar, pjulian@uns.edu.ar, pmandolesi@uns.edu.ar  Abstract−− A method for the calculation of the delay between two digital signals with central fre-quencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to de-termine the bearing angle of a sound source. Com-puting accuracy is tested against a previous imple-mentation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx®  FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations. Keywords−− Verilog, FPGA, low power, digital CMOS VLSI. I. INTRODUCTION Methods for the detection of sound sources have been widely studied, including the use of complex techniques such as Independent Component Analysis, Cross-correlation analysis (Carter, 1987; Knapp and Carter, 1976; Riddle, 2004), Gradient Flow techniques (Stana-cevic and Cauwenberghs (2005), and the emulation of the human hearing cochlea (Shamma et al., 1986; Laz-zaro and Mead, 1989; Horiuchi, 1995), some of which have been successfully implemented in analog and digi-tal VLSI circuits (Lazzaro and Mead, 1989; Horiuchi, 1995; Harris et al., 1999; Grech et al., 1999; van Schaik and Shamma, 2004). There are only a few cases in the literature where low power integrated circuits have been implemented for this task. Van Schaik and Shamma (2004) implemented an integrated circuit (IC) based on an analog cochlea using a 0.5μm process in an area of 5 mm2. In this case, the power dissipation depends strongly on the input signals. With no activity, the co-chlear channels dissipate 400 μW; for a time delay of 100 μs (corresponding to a 77 ˚ angle incoming signal), the power dissipated is 1.85 mW. Stanacevic and Cau-wenberghs (2005) implemented a 3 mm by 3 mm, 0.5μm CMOS technology IC with a method based on analog processing at a sampling rate of 16 kHz, which discriminates 2 µs with a power consumption of 32 μW. A third implementation, proposed in Julián et al. (2004) and successfully implemented in Julián et al. (2006), is based on a cross-correlation derivative algorithm. This method features an accuracy of one degree for angles in the range = [0,50] U [+130,+180] for signals between [20 Hz, 200 Hz], using two detectors (i.e. four micro-phones) to cover the whole 360 degrees without accu-racy loss. The integrated circuit (IC) designed by Julián et al. (2006), allows for this with less than 600μW of power dissipation (for a full quadrant bearing estima-tion) on a 0.35μm technology with measures of 2 mm by 2.4 mm. An alternative method for the estimation of such an-gle is proposed in this paper in order to reduce power dissipation still further, while keeping calculation per-formance. The problem is to determine the direction of a sound source picked by an array of microphones such as the one in Fig. 1. The digital signals are provided from this array after being conveniently conditioned. The cross-correlation derivative (CCD) approach is a varia-tion of the standard time-domain cross-correlation be-tween two signals. The CCD algorithm works with a one bit discrete quantization of the input signals, and therefore, reduces drastically the complexity of the re-sulting digital circuitry. Another feature is that the spa-tial derivative of the cross-correlation is calculated in-stead of the cross-correlation itself. Calculation of the CCD results in an activity reduction of a thousand times in the digital circuitry. In the case of the standard cross-correlation approach, once the partial correlations are calculated, the maximum needs to be evaluated which requires a dedicated stage. In the CCD, it is only neces-sary to locate a change in the output value of the partial correlations (which are either 1 or 0), making this task trivial: one only needs to detect transitions of the input signals. The strategy proposed in this paper is to use a single counter for delay measurement together with an adap-tive closed loop system. The closed loop guarantees stability, and also a convergence of the counter count to the delay under measurement. The reduction of power consumption is a consequence of the reduction in size of the circuitry. In fact, just one counter is needed as op-posed to the 104 10-bit counters used in the implemen-tation proposed by Julián et al. (2006).  The paper is organized as follows. Section II de-scribes the Verilog HDL front-end implementation of the proposed structure for the detection of transitions 

A Verilog HDL digital architecture for delay calculation

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A Verilog HDL digital architecture for delay calculation

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