A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed

Asenov, A.

Barker, J.R.

Kaya, S.

Roy, S.

English

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RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation

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      Roy, S. and Kaya, S. and Asenov, A. and Barker, J.R. (1999) RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation. In, International Conference on Simulation of Semiconductor Processes and Devices., 6-8 September 1999, pages pp. 147-150, Kyoto, Japan.         http://eprints.gla.ac.uk/3025/     Glasgow ePrints Service http://eprints.gla.ac.uk 7-1 2 RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo Simulation S. Roy, S. Kaya, A. Asenov and J. R. Barker Device Modelling Group Department of Electronics and Electrical Engineering, Rankine Building, University of Glasgow, Glasgow G12 8LT, United Kingdom Abstract A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for  complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed. 1. Introduction The rapidly expanding wireless communications industry has highlighted the need to integrate microwave signal processing functions onto conventional Si chips, reducing system component count and complexity [I]. To fulfil this need there is an urgent requirement for accurate analysis of Si and strained Si (on SiGe virtual substrates) MOSFET performance for RF device design, accounting for both non-equilibrium channel carrier transport in deep submicron devices and realistic device parasitics. RF analysis requires a realistic simulation geometry and correct handling of device parasitics. We have developed a comprehensive RF analysis methodology based on transient ensemble Monte Carlo simulation to study and compare the high frequency performance of Si and strained Si:SiGe MOSFETs. In addition to detailed Monte Carlo analysis of charge transport, the finite element simulator H2F [2] uses quadrilateral elements to accurately describe complex device geometries (including gate and contact geometries). Originally developed to analyse 111-V devices it has been .extensively modified to handle both Si and strained Si on relaxed SiGe buffers. 2. RF Analysis Methodology We perform time domain Monte Carlo RF analysis to model RF performance. Step changes are applied to first the gate, and then the drain contacts of a device under simulation after allowing for 2.0 ps settling time and 6.0 ps to determine device steady state. Gate and drain transient currents are recorded. The Ramo-Shockley formalism is implemented to reduce statistical noise in these transient terminal currents [3].  As laid out in fig. 1, Fourier transforming the transient terminal currents provides the complex y-parameters, from which we may obtain the cut-off frequency f ,  and, after a further transformation to s-parameters, the maximum frequency of oscillation, f,,,,,, . However, the 2D domain of Monte Carlo simulation is chosen to minimise computational effort in order to improve the speed of analysis. The access resistances (RA,  and R,, in fig. 1) are included, whilst the gate and contact impedances ( R g ,  Lg ,  R c ,  L, and L, in fig. 1) are not. The small signal equivalent circuit for the active portion of the device must be obtained by a further transformation to z-parameters, allowing simple removal of access resistances, and then retransformation back to y-parameters 147 Fourier Irm~s6rm (,..-F2”! my”’”-:=- . ,  .b.. ’: .............. .-• s Fig. 1 RF analysis of Monte Carlo transient response and extraction of both Figures of Merit and Small Signal Equivalent Circuit Parameters. before analytical small signal equivalent circuit extraction. To obtain figures of merit for a ‘real’ device the z-parameters are augmented with the contact impedances. From these augmented Zrrn‘ an equivalent set of retransformations gives F‘ and thence Srrn‘ from which the figures of merit fpr and fz’ can be extracted. Note the inclusion of the gate-bulk capacitance and substrate resistance CB6, RArrb in the equivalent circuit. While Cgb for the active gate region is negligible due to the shielding effect of the inversion layer under normal device operation, the gate-bulk capacitance of the gate contacts becomes significant for typical multi-fingered RF CMOS style structures [4]. Inclusion of Cgb, makes the small signal equivalent circuit of fig. 1 more appropriate to the devices described in fig. 2(c,d). 3. Devices Structures Analysed Fig. 2(a) describes a strained Si:SiGe T-gate MOSFET presently under construction at the University of Glasgow. To avoid the onset of parallel conduction at the oxide interface the spacer and supply layers should be as thin as possible. However practical limitations are set both by the need to avoid supply layer dopants diffusing into the channel, and by present oxide growth technology. 1D Poisson-Schrodinger simulation suggests that the operating regime of this device will be constrained by parallel conduction. Fig. 2(b) describes a 0.12 pm gate length (0.1 pm effective channel length) Si:SiGe MOSFET incorporating best practice design techniques from the 111-V RF device L 200nm SiGe relaxed buffer SiGe graded buffer \S,Ge buffer i 160 nm (a) (b) (c) (4 Fig. 2 Device-structures of the various Si and SiGe RF MOSFETs studied in this work: (a) realistic SiGe MOSFET, (b) SiGe modulation doped MOSFET, (c) state-of-the-art Si MOSFET, (d) RF enhanced Si MOSFET. 148 community. Although technologically challenging, analysis of this FET is expected to show the performance potential of Si:SiGe. Fig. 2'(c) shows an aggressively scaled state-of-the-art silicon device, a CO salicided T- gate style RF device with measured f~ = 65 GHz, fmax = 70 GHz developed by Toshiba [5] .  Fig.2(d) is a Si MOSFET presently under investigation at the University of Glasgow to investigate RF enhancements to present Si processing technology. 4. Results and Discussion The Monte Carlo nature of the analysis methodology accounts for non-equilibrium transport effects in the active regions of short channel devices. Fig. 3 shows the higher drift velocity and improved effective channel length in the 100 nm strained Si channel of device (b) compared with that of device (a). Note that the high drift velocity exhibited by device (d) is partially because of its shorter effective channel length, but also due to exclusion of surface roughness (interface) scattering from the Si model. 2 s  I7"" 300 - 8 200 8 100 -0.2 -0.1 0.0 0.1 0 1 . 2  3 4 5 x (w) Gate Resistance (52) Fig. 3 Electron drift velocities in the channels Fig. 4 Simulated variation in the A,,,, of device of devices (a,b,d). V ,  = 1.5V with V ,  chosen for (c) as a function of gate and source / drain contact maximum transconductance. In each case the RH resistances. edge of the gate metal is at x = 0. 10.0 n E 7.5 2 Y E 5 5.0 2 2.5 U G ._ 0.0 Figures of Merit (a) (b) (c) (d) gate, source and drain resistance 5 Q  fT (GHz)  43/34 71 80 85 fmaw(GHz) 77/49 66 100 63 -1.0 0.0 1.0 2.0 3.0 Gate Voltage (V) Fig. 5 Transfer characteristics of devices Table 1 RF figures of merit for devices (a,b,c,d) (a,b,c,d). Monte Carlo simulation for 6.0 ps after biased about maximum transconductance and 2.0 ps settling time. V,  = 1.5V. Device width of obtained from a simulated 5.0 ps transient lOOpm assumed. Traces (d,c) have been response to AV,> = 0.3V, AV,  = 0.2V. Device successively offset by -1 .OV for clarity. (a) outwithiwithin parallel conduction regime. 149 Fig. 4 shows the variation of A,,,, in device (c) over a range of low resistance gate and source/drain contacts. The interaction of even nominal resistances with device parasitic capacitances have a marked effect on its figures of merit, emphasising the need to correctly include both transport and parasitics in an RF analysis methodology. Fig. 5 and Table 1 present the transfer characteristics (including maximum transconductance) and figures of merit obtained from RF analysis of devices (a) to (d). Single fingered structures with negligible C,, and contact resistances of 5Q are assumed. The expected limitations of device structure (a) are obvious. A parasitic conduction layer at the oxide interface forms only 0.5V above threshold, dropping the maximum g,,, to 250mS/mm. Even before the formation of this layer the T-gate structure fails to control the effective channel length of the device, resulting in a reduced channel velocity and lower f,. Devices (b), (c) and (d) all exhibit similar transconductances, and thus broadly similar f, values, accepting that simulation of pure Si devices overestimates f, due to the omission of interface scattering from the Monte Carlo model. In addition f, of the physically measured devices is lower due to their increased gate resistance (> 30 Q). It is clear from fig. 4 thati,, values are critically dependant on device parasitics, and this is emphasised by device (c) where a radically different contact geometry leads to increased J,,,,. In conclusion, we have presented an RF analysis methodology for Si and SiGe MOSFETs based on Monte Carlo simulation and accounting for both non-equilibrium carrier transport and realistic device parasitics. The methodology has been successfully applied to a range of existing and proposed device designs. References J. Burghartz, “Silicon RF Technology - The Two Generic Approaches” Proceedings of the 2 7th European Solid-state Device Research Con5 ESSDERC197, 143 (1997) S. Babiker, A. Asenov, N. Cameron, S.P. Beaumont, and J.R Barker, “Complete Monte Carlo RF Analysis of ‘Real’ Short-Channel Compound FETs” IEEE Trans. Electron Devices, 45 1644 (1998) H. Kim, H.S. Min, T.W. Tang, Y.J. Park, “An Extended Proof of the Ramo- Shockley Theorem” Solid State Electronics, 43 125 1 (1991) E. Morifuji, H.S. Momose, T. Ohguro, T. Yoshimoto, H. Kimijima, F .  Matsuoka, M. Kinugawa, K. Katsumata, H. Iwai, “Future perspective and scaling down’roadmap for RF CMOS” IEEE Symposium on VLSI Technology 163 (1999) T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimijima, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata and H. Iwai, “High performance RF characteristics of raised gate/source/drain CMOS with CO salicide”, IEEE Symposium on VLSI Technology 136 (1998) 150 

Future perspective and scaling down’roadmap for RF CMOS”

Silicon RF Technology - The Two Generic Approaches” Proceedings of the 2 7th European Solid-state Device Research Con5 ESSDERC197, 143

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RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation

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