A high-resolution hold-off time control circuit for Geiger-mode avalanche photodiodes (GM-APDs) that enables linear changes to the hold-off time from several nanoseconds to microseconds is presented. The resolution of the hold-off time can be varied from nanoseconds to tens of nanoseconds with a range up to 1.2 μs to cater for a variety of GM-APDs. This circuit allows setting of the optimal `afterpulse-free' hold-off time for any GM-APD through digital inputs or additional signal processing circuitry. The layout area is 95 μm × 55 μm which makes it suitable for use with APD arrays. The APD is automatically reset following the end of the hold-off period

Deng, Shijie

Morrison, Alan P.

Cork Open Research Archive

Title High resolution hold-off time control circuit for Geiger-mode avalanchephotodiodesAuthor(s) Deng, Shijie; Morrison, Alan P.Publication date 2012-05Original citation Deng, S. and Morrison, A. P. (2012) 'High resolution hold-off timecontrol circuit for Geiger-mode avalanche photodiodes',  MIXDES 2012,19th International Conference Mixed Design of Integrated Circuits andSystems, Warsaw, Poland, 24 - 26 May. Available online:https://ieeexplore.ieee.org/document/6225758/Type of publication Conference itemLink to publisher'sversionhttps://ieeexplore.ieee.org/document/6225758/Access to the full text of the published version may require asubscription.Rights © 2012 by Department of Microelectronics & Computer Science,Technical University of Lodz. Published by IEEE.Item downloadedfromhttp://hdl.handle.net/10468/6395Downloaded on 2019-01-07T06:02:05Z High-resolution Hold-off Time Control Circuit for Geiger-mode Avalanche Photodiodes  Shijie Deng Department of Electrical and Electronic Engineering and Tyndall National Institute University College Cork, Ireland. Cork, Ireland shijie.deng@tyndall.ie Alan P. Morrison Department of Electrical and Electronic Engineering and Tyndall National Institute University College Cork, Ireland. Cork, Ireland a.morrison@ucc.ie    Abstract—A high-resolution hold-off time control circuit for Geiger-mode avalanche photodiodes (GM-APDs) that enables linear changes to the hold-off time from several nanoseconds to microseconds is presented. The resolution of the hold-off time can be varied from nanoseconds to tens of nanoseconds with a range up to 1.2 µs to cater for a variety of GM-APDs. This circuit allows setting of the optimal 'afterpulse-free' hold-off time for any GM-APD through digital inputs or additional signal processing circuitry. The layout area is 95 µm × 55 µm which makes it suitable for use with APD arrays. The APD is automatically reset following the end of the hold-off period.  Index Terms—Geiger-mode avalanche photodiodes, Hold-off time, High-resolution, Afterpulsing I. INTRODUCTION  Geiger-mode avalanche photodiodes (GM-APD) are commonly used where high sensitivity low-light intensity detection is required. Typical applications include DNA sequencing, quantum key distribution, LIDAR and medical imaging. In the Geiger-mode, the APD is biased above its breakdown voltage. When a photon is absorbed by the APD an avalanche event is triggered and the event is counted. After every avalanche event, some residual charge is stored in traps in the APD. The release of this stored charge when the GM-APD is active often leads to an avalanche current correlated to a previous avalanche event, but not related to a new photon arrival. This is an unwanted source of noise and is typically termed "afterpulsing". The afterpulsing is reduced by waiting for all the trapped charge to dissipate before resetting the GM-APD. This is generally achieved using an appropriate control circuit that quenches the APD avalanche current by lowering it’s bias voltage below the breakdown voltage. The APD is kept in the OFF state for fixed  period of time, called the hold-off time, before resetting the device to its original bias voltage to await the next avalanche event. If the hold-off time is less than the mean trap lifetime then afterpulsing will significantly affect the photon counting statistics. If the hold-off time is much greater than the mean trap lifetime then the counting rate will be limited and the validity of the counting statistics will also be affected. The hold-off time must be set according to the nature and density of the traps present in a particular device to minimize the significance of afterpulsing.    Fig. 1. Schematic and the performance of the monostable  The most popular method used for setting hold-off time is to use monostables [1], [2], [3], [4]. The monostable can offer a wide range of hold-off times (from nanoseconds to microseconds), however adjustment of the hold-off time is non-linear and difficult to control, as illustrated in Fig. 1. In [5], the delay line technique is used to set the hold-off time, as shown in Fig. 2. This circuit uses separate ramp voltage generators that create pre-defined pulse-widths for setting the hold-off time. This technique makes it easier to select an appropriate hold-off time, but this design is costly with increased layout area and complexity. In addition, the layout area required with this approach increases with each discrete hold-off time added. An additional disadvantage to all the traditional techniques for setting the hold-off time is the need for an additional monostable or pulse generator to reset the APD, which adds to the complexity of the control circuit.   Fig. 2. Diagram of delay line technique from [5]  This paper describes a high-resolution hold-off time control circuit that allows linear setting of the hold-off time from several nanoseconds to microseconds. Its small size, reduced complexity and automatic reset makes it attractive for use with a wide variety of GM-APD architectures. The step-size of the hold-off time can be altered from several nanoseconds to dozens of nanoseconds by varying the period of the external clock. This clock controls a counter through which the hold-off time can be varied linearly. The circuit layout, implemented using L-Foundry 0.15 µm CMOS process, has dimensions of only 95 µm × 55 µm. This relatively small size facilitates its integration with arrays of GM-APDs.  This circuit, shown in Fig. 3,  will reset the APD automatically at the end of the hold-off period without the requirement for an additional monostable or delay line circuit. II. CIRCUIT DESCRIPTION Fig. 3 shows the block diagram of the high-resolution hold-off time control circuit. The non-inverting input of the comparator is connected to the anode of the APD, which is biased at voltage between the avalanche breakdown voltage, Vbreak, to (Vbreak +Vdd). The comparator is used to sense the avalanche current at the anode of the APD which also has an inverse output, compo , that is connected to an external bond pad for readout. One PMOS and one NMOS transistor are used as the switches for quenching or resetting the APD. An external clock signal provides the counting clock during the hold-off period and a counter is used to control the hold-off time. Initially, when there is no avalanche current, compo is low, the external clock is blocked and the 6-bit counter is reset to 0 ("000000"), both PMOS and NMOS transistors are turned off. When an avalanche event happens in the APD, current flows through the load resistor, RL, and the voltage increases at the anode of APD. The comparator senses the voltage rise and compo goes from low to high. Qp goes low to turn on the PMOS transistor and the anode of the APD is connected to Vdd for quenching. Meanwhile, the counter is receiving clocks from the external clock (Clk_in).   Fig. 4. Schematic of the 6-bit synchronous binary counter used   Fig. 3. Block diagram of the high-resolution hold-off time control circuit The counter used here is a 6-bit synchronous binary counter which consists of 6 J-K flip-flops with the clock signal connected to the clock input of every flip-flop and the J and K inputs are tied together, see Fig. 4. The J and K inputs of the first flip-flop are connected to Vdd; the J and K inputs of the other flip-flops are connected to the output Q of each front end. When the reset signal compo is high, the counter receives clocks from Clk_in and counts upwards from 0 ("000000") to 63 ("111111"). Each output of the counter is connected to one input of an XNOR gate. The other input of the XNOR is connected to an external input (controlled by end user). When the output of the counter is equal to the external inputs, all the outputs of the XNOR gates go to logic "1" (high). Then Rn goes high which makes Qp go high to stop the hold-off process and turn on the NMOS transistor to reset the APD (two buffers are used here to make sure the reset process starts after the hold-off process is finished). At this time, the ‘Node A’ goes low to stop the clock to the counter and the counter is stopped. This then makes Rn remain high for resetting. When the anode of the APD is reset back to ground, compo is low, the Clk_in is blocked again and the counter is reset to 0 ("000000"). Now the outputs of the counter do not match the external inputs, Rn goes low and the NMOS transistor is turned off to complete the reset process. The APD is then ready to detect the next photon. By setting the external inputs, the counting number can be determined and the hold-off time can be altered. The step resolution is decided by the counting speed, which depends on the period of the external clock Clk_in. III. LAYOUT AND SIMULATIONS The layout of the proposed circuit was completed using L-Foundry 0.15 µm CMOS process and is illustrated in Fig.5. The overall chip dimension is about 700 µm × 700 µm which mostly occupied by the bond pads. The dimensions of IC core (without bond pads) are 95 µm × 55 µm. All the simulations reported are post-layout simulations.  Fig. 5. Layout of the proposed circuit  For circuit simulations, a linear model of the GM-APD is used, as illustrated in Fig. 6 [6]. Vb is a voltage source that represents the breakdown voltage, which is set at 27 V. The bias voltage is set to 30 V. Rd is the internal resistance, which is set to 250 Ω. Cd, is the junction capacitance, which is set to 2 pF. The simulations were run in the Cadence design environment with Vdd = 3.3 V.   Fig. 6. Simulation model of the GM-APD   Fig. 7. Example of the circuit operation when the external inputs are set to 30 ("011110") Fig. 7 shows an example of the circuit operation when the external inputs are set to 30 ("011110"). The period of external clocks is set to 2 ns. As can be seen from the figure, at 5 ns when a photon absorbed, the comparator senses the voltage change from the anode of the APD and Qp goes low for quenching. Meanwhile, the external clock is not blocked and providing the clocks to the counter. The 6-bit counter counts upwards from 0 ("000000") at a rate set by the external clocks (here is set to 2 ns). When the outputs of the counter match the external inputs, which in this case are set to 30 ("011110"), Rn goes high which makes Qp go high to stop the hold-off process and turn on the NMOS transistor to reset the APD. At this time, the clocks to the counter are blocked and the counter is stopped thereby making Rn high for resetting the APD. When the anode of the APD is set back to ground, the counter is reset to 0 ("000000") and Rn goes low to stop the reset process. In this way, with the external inputs of 30 ("011110"), the hold-off time is set to around 60 ns. Fig. 8 shows the simulation results of varying the external input codes versus the resultant hold-off time. It shows when the input code increases from 1 ("000001") to 63 ("111111") the hold-off time linearly increases to more than 120 ns with a step resolution of about 2 ns.   Fig. 8. External input codes versus resultant hold-off time when the step resolution is set to 2 ns  Fig. 9 shows the setting range of the hold-off time for different step resolutions. As can be seen from the figure, when the step resolution is varied from 2 ns to 20 ns, the range of the hold-off can be altered by more than a microsecond.   Fig. 9. Setting range of the hold-off time for different step resolutions IV. CONCLUSION A high-resolution hold-off time control circuit for Geiger-mode avalanche photodiodes is described in this paper. With this circuit, the hold-off time can be linearly varied from several nanoseconds to microseconds with a user-set resolution. The optimal 'afterpulse-free' hold-off time for any GM-APD can be easily set through the circuit's digital inputs or via an additional signal processing circuit. A layout of this circuit was completed using a conventional CMOS process, resulting in a small layout area that makes it suitable for integration with arrays of GM-APDs. The circuit also incorporates a facility designed to reset the APD automatically at the end of the hold-off time that further simplifies the control for the end-user. ACKNOWLEDGMENT This work was supported by Science Foundation Ireland under grant 07/SRC/I1173. REFERENCES [1] F. Zappa, M. Ghioni, S. Cova, C. Samori and A.C. Giudice, “An integrated active-quenching circuit for single-photon avalanche diodes,” IEEE Transactions on Instrumentation and Measurement, vol.49, no.6, pp.1167-1175, Mar.2000. [2] F. Zappa, A. Lotito, A.C. Giudice, S. Cova and M. Ghioni, "Monolithic active-quenching and active-reset circuit for single-photon avalanche detectors,"  IEEE Journal of Solid-State Circuits, vol.38, no.7,  pp.1298-1301, Jul.2003.  [3] S. Tisa, F. Guerrieri and F. Zappa, "Variable-load quenching circuit for single-photon avalanche diodes," Optics Express, vol.16, no.3, pp. 2232-2244, Feb.2008. [4] Rosario Mita and Gaetano Palumbo, "High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes," IEEE Transactions on Instrumentation and Measurement, vol. 57, no. 3, pp.543-547, 2008. [5] D. Cronin and A. P. Morrison, "Intelligent System for Optimal Hold-Off Time Selection in an Active Quench and Reset IC," IEEE Journal of Selected Topics in Quantum Electronics, vol.13, no.4, pp.911-918, Jul./Aug. 2007. [6] .S. Cova, M. Ghioni, A. Lacaita, C. Samori, and F. Zappa, "Avalanche photodiodes and quenching circuits for single-photon detection," Applied Optics, vol.35, no.12, pp.1956-1976, 1996.   

High resolution hold-off time control circuit for Geiger-mode avalanche photodiodes

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High resolution hold-off time control circuit for Geiger-mode avalanche photodiodes

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