Piece-wise-linear ramp ADC for CMOS imager sensor and calibration techniques

Abstract

International audienceIn this paper, a 10-bitdigitalCorrelated DoubleSampling (CDS)high-speed CMOS Image Sensordesignedin 65nm BSI technologyfor a 1.1μm pixelis proposed.Thereadoutarchitecture has been developed to read a 13Mpixsensor (4248 x 3216) at 55frames/s,requiringa row time of5.5μs.Thereadout is based on a Piece-Wise Linear (PWL)ramp generatorimplementing anI/C structure.Twoinnovativecalibrationtechniquesfor output datalinearization are investigate