There is currently a strong focus across the technological landscape to create machines capable of performing complex, objective based tasks in a manner similar to, or superior to a human. Many of the methods being explored in the machine intelligence space require large sets of labeled data to first train, and then classify inputs. Hierarchical Temporal Memory (HTM) is a biologically inspired machine intelligence framework which aims to classify and interpret streaming unlabeled data, without supervision, and be able to detect anomalies in such data.
In software HTM models, increasing the number of “columns” or processing elements to the levels required to make meaningful predictions in complex data can be prohibitive to analyzing in real time. There exists a need to improve the throughput of such systems. HTMs require large amounts of data available to be accessed randomly, and then processed independently. FPGAs provide a reconfigurable, and easily scalable platform ideal for these types of operations. One of the two main components of the HTM architecture is the “spatial pooler”. This thesis explores a novel hardware implementation of an HTM spatial pooler, with a boosting algorithm to increase homeostasis, and a novel classification algorithm to interpret input data in real time. This implementation shows a significant speedup in data processing, and provides a framework to scale the implementation based on the available hardware resources of the FPGA
