Fanucci L.

Petri E.

Saponara S.

Undetermined

The paper presents a multi-processor architecture for real-time and low-power image and video enhancement applications. Differently from other state-of-the-art parallel architectures the proposed solution is composed of heterogeneous tiles. The tiles have computational and memory capabilities, support different algorithmic classes and are connected by a novel Network-on-Chip (NoC) infrastructure. The proposed packet-switched data transfer scheme avoids communication bottlenecks when more tiles are working concurrently. The functional performances of the NoC-based multi-processor architecture are assessed by presenting the achieved results when the platform is programmed to support different enhancement algorithms for still images or videos. The implementation complexity of the NoC-based multi-tile platform, integrated in 65 nm CMOS technology, is reported and discusse

SAPONARA, SERGIO

FANUCCI, LUCA

Archivio della Ricerca - Università di Pisa

A multi-processor NoC-based architecture for real-time image/video enhancement

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https://www.openaccessrepository.it/record/23128/files/fulltext.pdf

A multi-processor NoC-based architecture for real-time image/video enhancement

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Archivio della Ricerca - Università di Pisa

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