A fault tolerant adjustable speed drive (ASD) topology is introduced in this work. A conventional ASD topology is modified to address: a) drive vulnerability to semiconductor device faults b) input voltage sags c) motor vulnerability to effects of long leads and d) achieve active minimization of common mode (CM) voltage applied to the motor terminals. These objectives are attained by inclusion of an auxiliary IGBT inverter leg, three auxiliary diodes, and isolation - reconfiguration circuit. The design and operation of the proposed topology modifications are described for different modes; (A) Fault mode, (B) Auxiliary Sag Compensation (ASC) mode and (C) Active Common Mode Suppression mode. In case of fault and sag, the isolation and hardware reconfiguration are performed in a controlled manner using triacs/anti-parallel thyristors/solid state relays. In normal operation, the auxiliary leg is controlled to actively suppress common mode voltage. For inverter IGBT failures (short circuit and open circuit), the auxiliary leg is used as a redundant leg. During voltage sags, the auxiliary leg along with auxiliary diodes is operated as a boost converter. A current shaping control strategy is proposed for the ASC mode. A detailed analysis of common mode performance of the proposed topology is provided and a new figure of merit, Common Mode Distortion Ratio (CMDR) is introduced to compare the attenuation of common mode voltage with that of a conventional ASD topology for three different modulation strategies. The output filter design procedure is outlined. A design example is presented for an 80 kW ASD system and simulation results validate the proposed
auxiliary leg based fault tolerant scheme. Experimental results from a scaled prototype rated at 1 hp prototype also confirm the operation. The common mode analysis is also validated with the experimental results
