The interconnect layouts of chips can be modeled by large resistor networks. In order to be able to
speed up simulations of such large networks, reduction techniques are applied to reduce the size of the networks. For some class of networks, an existing reduction strategy does not provide sufficient reduction in terms of the number of resistors appearing in the final network. In this paper we propose an approach for obtaining a further reduction in the amount of resistors. The suggested approach improves sparsity of the conductance matrix by neglecting resistors which do not contribute significantly to the behavior of the circuit. Explicit error bounds, which give an opportunity to control the errors due to approximation, have been derived. Numerical examples show that the suggested approach appears promising for multi-terminal resistor networks and, in combination with the existing reduction strategy, leads to better reduction
