Virtual synaptic interconnect using an asynchronous network-on-chip

Abstract

Abstract—Given the limited current understanding of the neural model of computation, hardware neural network archi-tectures that impose a specific relationship between physical connectivity and model topology are likely to be overly restric-tive. Here we introduce, in the SpiNNaker chip, an alternative approach: a mappable virtual topology using an asynchronous network-on-chip (NoC) that decouples the “logical ” connectivity map from the physical wiring. Borrowing the established digital RAM model for synapses, we develop a concurrent memory access channel optimised for neural processing that allows each processing node to perform its own synaptic updates as if the synapses were local to the node. The highly concurrent nature of interconnect access, however, requires careful design of intermediate buffering and arbitration. We show here how a locally buffered, one-transaction-per-node model with multipl