The NULL Cycle Reduction (NCR) technique can be used to improve the performance of the NULL Convention Logic (NCL) circuit at the expense of power and area. However, by decreasing the supply voltage of certain components, the power of the NCR circuit can be reduced. Since NCR has increased performance, it could be possible to decrease the power while maintaining the original performance of the circuit. To verify this, the NCR circuit will be implemented using a 4-bit by 4-bit dual-rail multiplier as the test circuit. This circuit will be simulated in ModelSim to ensure functionality, synthesized into a Verilog netlist using Leonardo, and imported into Cadence to perform transistor-level simulations for power calculations. The supply voltage of the duplicated circuits will be decreased until the performance matches the design of the original multiplier, resulting in overall lower energy usage
